Travelled to:1 × China
2 × Canada
2 × USA
Collaborated with:J.Torrellas A.Ansari G.Karsai ∅ A.Vizhanyo F.Shi P.Jain N.P.Carter S.Borkar R.Cledat H.David D.Dunning J.B.Fryman I.Ganev R.A.Golliver R.C.Knauerhase R.Lethin B.Meister A.K.Mishra W.R.Pinfold J.Teller N.Vasilache G.Venkatesh J.Xu
Talks about:transform (3) architectur (2) refresh (2) comput (2) model (2) graph (2) chip (2) multiprocessor (1) bottleneck (1) hierarchi (1)
Person: Aditya Agrawal
DBLP: Agrawal:Aditya
Contributed to:
20142013
2004
2003
2003Wrote 6 papers:
- HPCA-2014-AgrawalAT #energy #locality #named #process
- Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules (AA, AA, JT), pp. 84–95.
- HPCA-2013-AgrawalJAT #multi #named
- Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies (AA, PJ, AA, JT), pp. 400–411.
- HPCA-2013-CarterABCDDFGGKLMMPTTVVX #architecture #named #ubiquitous
- Runnemede: An architecture for Ubiquitous High-Performance Computing (NPC, AA, SB, RC, HD, DD, JBF, IG, RAG, RCK, RL, BM, AKM, WRP, JT, JT, NV, GV, JX), pp. 198–209.
- GPCE-2004-VizhanyoAS #generative #performance #towards
- Towards Generation of Efficient Transformations (AV, AA, FS), pp. 298–316.
- AGTIVE-2003-KarsaiA #architecture #graph transformation #modelling
- Graph Transformations in OMG’s Model-Driven Architecture: (GK, AA), pp. 243–259.
- ASE-2003-Agrawal #graph grammar
- Graph Rewriting And Transformation (GReAT): A Solution For The Model Integrated Computing (MIC) Bottleneck (AA), pp. 364–368.