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Travelled to:
2 × Germany
3 × USA
Collaborated with:
D.Blaauw V.Zolotov K.Chopra S.B.K.Vrudhula F.Dartu
Talks about:
statist (5) time (3) use (3) circuit (2) analysi (2) optim (2) delay (2) bound (2) gate (2) multipl (1)

Person: Aseem Agarwal

DBLP DBLP: Agarwal:Aseem

Contributed to:

DAC 20052005
DATE 20052005
DAC 20042004
DAC 20032003
DATE 20032003

Wrote 5 papers:

DAC-2005-AgarwalCBZ #analysis #optimisation #statistics #using
Circuit optimization using statistical static timing analysis (AA, KC, DB, VZ), pp. 321–324.
DATE-2005-AgarwalCB #optimisation #statistics #using
Statistical Timing Based Optimization using Gate Sizing (AA, KC, DB), pp. 400–405.
DAC-2004-AgarwalDB #multi #statistics
Statistical gate delay model considering multiple input switching (AA, FD, DB), pp. 658–663.
DAC-2003-AgarwalBZV #bound #refinement #statistics
Computation and Refinement of Statistical Bounds on Circuit Delay (AA, DB, VZ, SBKV), pp. 348–353.
DATE-2003-AgarwalBZV #analysis #bound #statistics #using
Statistical Timing Analysis Using Bounds (AA, DB, VZ, SBKV), pp. 10062–10067.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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