Travelled to:1 × France
3 × Germany
3 × USA
Collaborated with:D.Blaauw S.B.K.Vrudhula A.Agarwal D.Sylvester R.R.Rao V.Zolotov S.Dasika R.Srinivasan B.Cline A.Torres S.Sundareswaran R.Gandikota M.R.Becer
Talks about:algorithm (2) statist (2) circuit (2) analysi (2) static (2) optim (2) delay (2) time (2) use (2) transistor (1)
Person: Kaviraj Chopra
DBLP: Chopra:Kaviraj
Contributed to:
2008
200720062005200520042004Wrote 8 papers:
- DATE-2008-ClineCBTS #modelling
- Transistor-Specific Delay Modeling for SSTA (BC, KC, DB, AT, SS), pp. 592–597.
- DAC-2007-GandikotaCBSB #analysis #set
- Top-k Aggressors Sets in Delay Noise Analysis (RG, KC, DB, DS, MRB), pp. 174–179.
- DATE-2006-RaoCBS #algorithm #fault #performance
- An efficient static algorithm for computing the soft error rates of combinational circuits (RRR, KC, DB, DS), pp. 164–169.
- DAC-2005-AgarwalCBZ #analysis #optimisation #statistics #using
- Circuit optimization using statistical static timing analysis (AA, KC, DB, VZ), pp. 321–324.
- DAC-2005-BlaauwC #tool support
- CAD tools for variation tolerance (DB, KC), p. 766.
- DATE-2005-AgarwalCB #optimisation #statistics #using
- Statistical Timing Based Optimization using Gate Sizing (AA, KC, DB), pp. 400–405.
- DAC-2004-ChopraV #algorithm #pseudo
- Implicit pseudo boolean enumeration algorithms for input vector control (KC, SBKV), pp. 767–772.
- DATE-v2-2004-DasikaVCS #framework
- A Framework for Battery-Aware Sensor Management (SD, SBKV, KC, RS), pp. 962–967.