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Travelled to:
7 × USA
Collaborated with:
L.T.Pileggi B.Tutuianu C.S.Amin Y.I.Ismail N.Menezes A.Agarwal D.Blaauw S.H.Choi K.Roy J.Qian L.T.Pillage K.Killpack U.Choudhury N.Hakim
Talks about:
delay (5) time (4) circuit (3) gate (3) approxim (2) statist (2) respons (2) analysi (2) moment (2) calcul (2)

Person: Florentin Dartu

DBLP DBLP: Dartu:Florentin

Contributed to:

DAC 20052005
DAC 20042004
DAC 20022002
DAC 19981998
DAC 19971997
DAC 19961996
DAC 19941994

Wrote 9 papers:

DAC-2005-AminID #approximate #using
Piece-wise approximations of RLCK circuit responses using moment matching (CSA, YII, FD), pp. 927–932.
DAC-2005-AminMKDCHI #analysis #how #question #statistics
Statistical static timing analysis: how simple can we get? (CSA, NM, KK, FD, UC, NH, YII), pp. 652–657.
DAC-2004-AgarwalDB #multi #statistics
Statistical gate delay model considering multiple input switching (AA, FD, DB), pp. 658–663.
DAC-2002-ChoiRD #generative
Timed pattern generation for noise-on-delay calculation (SHC, KR, FD), pp. 870–873.
DAC-1998-DartuP #analysis #named
TETA: Transistor-Level Engine for Timing Analysis (FD, LTP), pp. 595–598.
DAC-1997-DartuP #worst-case
Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling (FD, LTP), pp. 46–51.
DAC-1996-DartuTP #megamodelling #simulation
RC-Interconnect Macromodels for Timing Simulation (FD, BT, LTP), pp. 544–547.
DAC-1996-TutuianuDP #approximate
An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response (BT, FD, LTP), pp. 611–616.
DAC-1994-DartuMQP #performance
A Gate-Delay Model for high-Speed CMOS Circuits (FD, NM, JQ, LTP), pp. 576–580.

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