Travelled to:1 × France
2 × Germany
Collaborated with:C.A.Papachristou F.G.Wolff M.Nicolaidis S.L.Garverick
Talks about:error (2) soft (2) semiconductor (1) interact (1) asymmetr (1) present (1) correct (1) circuit (1) analysi (1) memori (1)
Person: Balkaran S. Gill
DBLP: Gill:Balkaran_S=
Contributed to:
200720062005Wrote 3 papers:
- DATE-2007-GillPW #fault #interactive #power management #symmetry
- Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA (BSG, CAP, FGW), pp. 1460–1465.
- DATE-2006-GillPW #analysis #fault #logic
- Soft delay error analysis in logic circuits (BSG, CAP, FGW), pp. 47–52.
- DATE-2005-GillNWPG #design #detection #performance
- An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories (BSG, MN, FGW, CAP, SLG), pp. 592–597.