BibSLEIGH — Christos_A

Travelled to:

11 × USA
6 × Germany
7 × France

Collaborated with:

M.Nourani F.G.Wolff J.Carletta B.S.Gill S.Chiu W.Jone H.Harmanani B.P.Singh D.J.Weyer D.R.McIntyre K.A.Ockunzzi Y.Alzazeri W.Zhao E.Ercanli H.Konuk A.Shankar S.Clay H.Rizk S.Yang M.Tabib-Azar F.Martin M.Spining M.Pereira S.Bhunia R.S.Chakraborty M.Nicolaidis S.L.Garverick M.J.Knieser M.S.Hashemian

Talks about:

test (13) synthesi (7) design (7) control (6) analysi (6) scheme (6) base (6) datapath (4) testabl (4) schedul (4)

Person: Christos A. Papachristou

DBLP: Papachristou:Christos_A=

Contributed to:

2015

2014

2008

2007

2006

2005

2004

2003

2001

2000

1999

1998

1997

1996

1993

1992

1991

1990

1989

Wrote 31 papers:

DATE-2015-HashemianSWWCP #array #authentication #robust #using: A robust authentication methodology using physically unclonable functions in DRAM arrays (MSH, BPS, FGW, DJW, SC, CAP), pp. 647–652.
DAC-2014-ShankarSWP #analysis #concept #design #specification: Ontology-guided Conceptual Analysis of Design Specifications (AS, BPS, FGW, CAP), p. 6.
DATE-2014-SinghSWPWC #analysis #specification: Cross-correlation of specification and RTL for soft IP analysis (BPS, AS, FGW, CAP, DJW, SC), pp. 1–6.
DATE-2008-WolffPBC #analysis #detection #problem #towards: Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme (FGW, CAP, SB, RSC), pp. 1362–1365.
DATE-2007-GillPW #fault #interactive #power management #symmetry: Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA (BSG, CAP, FGW), pp. 1460–1465.
DATE-2006-GillPW #analysis #fault #logic: Soft delay error analysis in logic circuits (BSG, CAP, FGW), pp. 47–52.
DATE-2005-GillNWPG #design #detection #performance: An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories (BSG, MN, FGW, CAP, SLG), pp. 592–597.
DATE-v1-2004-WolffPM #hardware: Test Compression and Hardware Decompression for Scan-Based SoCs (FGW, CAP, DRM), pp. 716–717.
DATE-v2-2004-RizkPW #design #embedded #source code: Designing Self Test Programs for Embedded DSP Cores (HR, CAP, FGW), pp. 816–823.
DATE-2003-KnieserWPWM: A Technique for High Ratio LZW Compression (MJK, FGW, CAP, DJW, DRM), pp. 10116–10121.
DAC-2001-OckunzziP #algorithm: Test Strategies for BIST at the Algorithmic and Register-Transfer Levels (KAO, CAP), pp. 65–70.
DAC-2001-YangPT #bound: Improving Bus Test Via IDDT and Boundary Scan (SYY, CAP, MTA), pp. 307–312.
DAC-2000-NouraniCP: Synthesis-for-testability of controller-datapath pairs that use gated clocks (MN, JC, CAP), pp. 613–618.
DATE-2000-CarlettaPN #analysis #detection #fault #using: Detecting Undetectable Controller Faults Using Power Analysis (JC, CAP, MN), pp. 723–728.
DAC-1999-PapachristouMN #testing: Microprocessor Based Testing for Core-Based System on Chip (CAP, FM, MN), pp. 586–591.
DATE-1999-CarlettaNP #synthesis #testing: Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs (JC, MN, CAP), pp. 278–282.
DATE-1999-PapachristouA #design #distributed: A Method of Distributed Controller Design for RTL Circuits (CAP, YA), pp. 774–775.
DATE-1998-NouraniP #fault #testing: A Bypass Scheme for Core-Based System Fault Testing (MN, CAP), pp. 979–980.
DATE-1998-ZhaoP #self #source code #testing: Testing DSP Cores Based on Self-Test Programs (WZ, CAP), pp. 166–172.
DAC-1997-NouraniCP #fault #testing: A Scheme for Integrated Controller-Datapath Fault Testing (MN, JC, CAP), pp. 546–551.
EDTC-1997-NouraniP #analysis #behaviour #using: Structural BIST insertion using behavioral test analysis (MN, CAP), pp. 64–68.
DAC-1996-ErcanliP #scheduling #synthesis: A Register File and Scheduling Model for Application Specific Processor Synthesis (EE, CAP), pp. 35–40.
DAC-1996-PapachristouSN #design #effectiveness #multi #power management: An Effective Power Management Scheme for RTL Design Based on Multiple Clocks (CAP, MS, MN), pp. 337–342.
DAC-1993-NouraniP #algorithm #estimation #layout: A Layout Estimation Algorithm for RTL Datapaths (MN, CAP), pp. 285–291.
DAC-1993-PapachristouHN #approach #synthesis: An Approach for Redesigning in Data Path Synthesis (CAP, HH, MN), pp. 419–423.
DAC-1992-NouraniP #automation #scheduling #synthesis: Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems (MN, CAP), pp. 99–105.
DAC-1991-ChiuP #design #synthesis #testing: A Design for Testability Scheme with Applications to Data Path Synthesis (SC, CAP), pp. 271–277.
DAC-1991-PapachristouCH #design #self #synthesis: A Data Path Synthesis Method for Self-Testable Designs (CAP, SC, HH), pp. 378–384.
DAC-1990-PapachristouK #algorithm #linear #optimisation #scheduling: A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm (CAP, HK), pp. 77–83.
DAC-1989-JoneP #approach #clustering #coordination #generative #pseudo #testing: A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing (WBJ, CAP), pp. 525–534.
DAC-1989-JonePP #concurrent #testing: A Scheme for Overlaying Concurrent Testing of VLSI Circuits (WBJ, CAP, MP), pp. 531–536.