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Travelled to:
1 × USA
5 × France
5 × Germany
Collaborated with:
C.A.Papachristou B.S.Gill B.P.Singh D.J.Weyer D.R.McIntyre A.Shankar S.Bhunia S.Clay H.Rizk R.S.Chakraborty M.Nicolaidis S.L.Garverick M.J.Knieser M.S.Hashemian X.Wang S.Narasimhan A.R.Krishna S.Rajgopal T.Lee M.Mehregany
Talks about:
analysi (4) design (3) soft (3) compress (2) specif (2) detect (2) error (2) test (2) high (2) use (2)

Person: Francis G. Wolff

DBLP DBLP: Wolff:Francis_G=

Contributed to:

DATE 20152015
DAC 20142014
DATE 20142014
DATE 20112011
DATE 20082008
DATE 20072007
DATE 20062006
DATE 20052005
DATE v1 20042004
DATE v2 20042004
DATE 20032003

Wrote 11 papers:

DATE-2015-HashemianSWWCP #array #authentication #robust #using
A robust authentication methodology using physically unclonable functions in DRAM arrays (MSH, BPS, FGW, DJW, SC, CAP), pp. 647–652.
DAC-2014-ShankarSWP #analysis #concept #design #specification
Ontology-guided Conceptual Analysis of Design Specifications (AS, BPS, FGW, CAP), p. 6.
DATE-2014-SinghSWPWC #analysis #specification
Cross-correlation of specification and RTL for soft IP analysis (BPS, AS, FGW, CAP, DJW, SC), pp. 1–6.
DATE-2011-WangNKWRLMB #configuration management #using
High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switches (XW, SN, ARK, FGW, SR, THL, MM, SB), pp. 1065–1070.
DATE-2008-WolffPBC #analysis #detection #problem #towards
Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme (FGW, CAP, SB, RSC), pp. 1362–1365.
DATE-2007-GillPW #fault #interactive #power management #symmetry
Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA (BSG, CAP, FGW), pp. 1460–1465.
DATE-2006-GillPW #analysis #fault #logic
Soft delay error analysis in logic circuits (BSG, CAP, FGW), pp. 47–52.
DATE-2005-GillNWPG #design #detection #performance
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories (BSG, MN, FGW, CAP, SLG), pp. 592–597.
DATE-v1-2004-WolffPM #hardware
Test Compression and Hardware Decompression for Scan-Based SoCs (FGW, CAP, DRM), pp. 716–717.
DATE-v2-2004-RizkPW #design #embedded #source code
Designing Self Test Programs for Embedded DSP Cores (HR, CAP, FGW), pp. 816–823.
A Technique for High Ratio LZW Compression (MJK, FGW, CAP, DJW, DRM), pp. 10116–10121.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.