BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
6 × USA
Collaborated with:
M.I.Elmasry R.J.Gebotys S.Wiratunga
Talks about:
alloc (3) architectur (2) processor (2) synthesi (2) schedul (2) memori (2) optim (2) embed (2) vlsi (2) constrain (1)

Person: Catherine H. Gebotys

DBLP DBLP: Gebotys:Catherine_H=

Contributed to:

DAC 20012001
DAC 20002000
DAC 19971997
DAC 19921992
DAC 19911991
DAC 19881988

Wrote 6 papers:

DAC-2001-Gebotys #embedded #memory management
Utilizing Memory Bandwidth in DSP Embedded Processors (CHG), pp. 347–352.
DAC-2000-GebotysGW #architecture #power management
Power minimization derived from architectural-usage of VLIW processors (CHG, RJG, SW), pp. 308–311.
DAC-1997-Gebotys #energy #memory management #network #using
Low Energy Memory and Register Allocation Using Network Flow (CHG), pp. 435–440.
DAC-1992-Gebotys #embedded #scheduling
Optimal Scheduling and Allocation of Embedded VLSI Chips (CHG), pp. 116–119.
DAC-1991-GebotysE #architecture #scheduling #synthesis
Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis (CHG, MIE), pp. 2–7.
DAC-1988-GebotysE #design #synthesis #testing
VLSI Design Synthesis with Testability (CHG, MIE), pp. 16–21.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.