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Travelled to:
1 × France
1 × Germany
Collaborated with:
G.V.d.Plas P.Wambacq S.Donnay S.Bronckers G.Vandersteen Y.Rolain
Talks about:
methodolog (2) substrat (2) analysi (2) simul (2) nois (2) interconnect (1) experiment (1) interact (1) present (1) circuit (1)

Person: Charlotte Soens

DBLP DBLP: Soens:Charlotte

Contributed to:

DATE 20072007
DATE 20052005

Wrote 2 papers:

DATE-2007-BronckersSPVR #analysis #interactive #simulation #verification
Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO’s (SB, CS, GVdP, GV, YR), pp. 1520–1525.
DATE-2005-SoensPWD #analysis #simulation
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance (CS, GVdP, PW, SD), pp. 270–275.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.