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Travelled to:
4 × Germany
4 × USA
6 × France
Collaborated with:
P.Wambacq G.Vandersteen G.G.E.Gielen M.Engels I.Bolsens H.D.Man M.Badaroglu P.Dobrovolný G.V.d.Plas W.M.C.Sansen J.Craninckx W.Kruiskamp D.Leenaerts M.v.Heijningen Y.Rolain C.Soens R.Pintelon D.Linten M.Goffioul F.Verbeyst J.Vandenbussche F.Leyn W.Eberle H.Ziad W.v.Bokhoven K.Swings K.Tiri I.Verbauwhede J.Schoukens V.Gravot
Talks about:
high (7) substrat (6) analog (6) simul (6) level (6) nois (6) nonlinear (5) circuit (5) digit (5) suppli (4)

Person: Stéphane Donnay

DBLP DBLP: Donnay:St=eacute=phane

Contributed to:

DATE 20052005
DAC 20042004
DATE v1 20042004
DAC 20032003
DATE 20032003
DAC 20022002
DATE 20022002
DATE 20012001
DAC 20002000
DATE 20002000
DATE 19991999
DATE 19981998
ED&TC 19971997

Wrote 19 papers:

DATE-2005-SoensPWD #analysis #simulation
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance (CS, GVdP, PW, SD), pp. 270–275.
DAC-2004-PlasBVDWDGM #simulation
High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects (GVdP, MB, GV, PD, PW, SD, GGEG, HDM), pp. 854–859.
DATE-v1-2004-BadarogluWPDGM #reduction
Digital Ground Bounce Reduction by Phase Modulation of the Clock (MB, PW, GVdP, SD, GGEG, HDM), pp. 88–93.
DATE-v1-2004-VandersteenPLD #identification #linear
Extended Subspace Identification of Improper Linear Systems (GV, RP, DL, SD), pp. 454–459.
DAC-2003-CraninckxD #design #how #question
4G terminals: how are we going to design them? (JC, SD), pp. 79–84.
DATE-2003-DobrovolnyVWD #analysis #modelling
Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits (PD, GV, PW, SD), pp. 10624–10629.
DATE-2003-EberleVWDGM #automation #behaviour #modelling #simulation
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver (WE, GV, PW, SD, GGEG, HDM), pp. 10642–10649.
DAC-2002-BadarogluTDWMVG #optimisation #reduction #using
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients (MB, KT, SD, PW, HDM, IV, GGEG), pp. 399–404.
DATE-2002-GoffioulWVD #analysis #approach #architecture #using
Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach (MG, PW, GV, SD), pp. 352–356.
DATE-2002-VandersteenWDV #evaluation #performance
High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions (GV, PW, SD, FV), pp. 586–590.
DATE-2001-BadarogluHGDMGEB #generative #multi #scalability #simulation
High-level simulation of substrate noise generation from large digital circuits with multiple supplies (MB, MvH, VG, SD, HDM, GGEG, ME, IB), pp. 326–330.
DATE-2001-VandersteenWRSDEB #estimation #multi #performance
Efficient bit-error-rate estimation of multicarrier transceivers (GV, PW, YR, JS, SD, ME, IB), pp. 164–168.
DAC-2000-HeijningenBDEB #generative #power management #simulation
High-level simulation of substrate noise generation including power supply noise coupling (MvH, MB, SD, ME, IB), pp. 446–451.
DAC-2000-VandersteenWRDDEB #data flow #performance #simulation
A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers (GV, PW, YR, PD, SD, ME, IB), pp. 440–445.
DATE-2000-WambacqDDEB #communication #modelling
Compact Modeling of Nonlinear Distortion in Analog Communication Circuits (PW, PD, SD, ME, IB), pp. 350–354.
A Single-Package Solution for Wireless Transceivers (PW, SD, HZ, ME, HDM, IB), p. 425–?.
DATE-1998-VandenbusscheDLGS #design #interface #specification #top-down
Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon (JV, SD, FL, GGEG, WMCS), pp. 716–720.
EDTC-1997-DonnayGSKLB #interface #synthesis
High-level synthesis of analog sensor interface front-ends (SD, GGEG, WMCS, WK, DL, WvB), pp. 56–60.
EDAC-1994-DonnaySGSKL #automation #design
A Methodology for Analog Design Automation in Mixed-Signal ASICs (SD, KS, GGEG, WMCS, WK, DL), pp. 530–534.

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