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Travelled to:
2 × Germany
3 × France
4 × USA
Collaborated with:
G.G.E.Gielen P.Wambacq S.Donnay C.Soens E.Beyne P.Nuzzo P.Marchal G.Vandersteen W.M.C.Sansen M.Badaroglu H.D.Man C.Nani S.Saponara L.Fanucci S.Bronckers Y.Rolain F.D.Bernardinis L.V.d.Perre B.Gyselinckx P.Terreni J.Vandenbussche W.Daems A.v.d.Bosch C.D.Ranter B.D.Muer P.J.Vancorenland M.Steyaert P.Dobrovolný G.Eneman J.Cho V.Moroz D.Milojevic M.Choi K.D.Meyer A.Mercha T.Hoffmann
Talks about:
substrat (4) design (3) simul (3) nois (3) interconnect (2) methodolog (2) convert (2) analysi (2) applic (2) high (2)

Person: Geert Van der Plas

DBLP DBLP: Plas:Geert_Van_der

Contributed to:

DAC 20112011
DATE 20112011
DATE 20082008
DATE 20072007
DAC 20062006
DATE 20052005
DAC 20042004
DATE v1 20042004
DAC 20002000

Wrote 10 papers:

DAC-2011-BeyneMP #3d #development #integration
3D heterogeneous system integration: application driver for 3D technology development (EB, PM, GVdP), p. 213.
DATE-2011-EnemanCMMCMMBHP #estimation #multi
An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations (GE, JC, VM, DM, MC, KDM, AM, EB, TH, GVdP), pp. 505–506.
DATE-2008-NuzzoNSFP #design
Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications (PN, CN, SS, LF, GVdP), pp. 1390–1393.
DATE-2007-BronckersSPVR #analysis #interactive #simulation #verification
Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO’s (SB, CS, GVdP, GV, YR), pp. 1520–1525.
A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW (PN, GVdP, FDB, LVdP, BG, PT), pp. 873–878.
DATE-2005-SoensPWD #analysis #simulation
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance (CS, GVdP, PW, SD), pp. 270–275.
DAC-2004-PlasBVDWDGM #simulation
High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects (GVdP, MB, GV, PD, PW, SD, GGEG, HDM), pp. 854–859.
DATE-v1-2004-BadarogluWPDGM #reduction
Digital Ground Bounce Reduction by Phase Modulation of the Clock (MB, PW, GVdP, SD, GGEG, HDM), pp. 88–93.
DAC-2000-PlasVDBGS #design
Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter (GVdP, JV, WD, AvdB, GGEG, WMCS), pp. 452–457.
DAC-2000-RanterMPVSGS #automation #design #layout #named
CYCLONE: automated design and layout of RF LC-oscillators (CDR, BDM, GVdP, PJV, MS, GGEG, WMCS), pp. 11–14.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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