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Travelled to:
2 × USA
Collaborated with:
Y.Chang T.Ho S.Chen P.Lee H.Lee Y.Ho I.Lin C.Shen
Talks about:
rout (2) chip (2) architectur (1) multilevel (1) obstacl (1) design (1) assign (1) avoid (1) full (1) free (1)

Person: Chen-Feng Chang

DBLP DBLP: Chang:Chen=Feng

Contributed to:

DAC 20122012
DAC 20052005

Wrote 2 papers:

DAC-2012-LeeLHCCLS #design
Obstacle-avoiding free-assignment routing for flip-chip designs (PWL, HCL, YKH, YWC, CFC, IJL, CFS), pp. 1088–1093.
DAC-2005-HoCCC #architecture #multi
Multilevel full-chip routing for the X-based architecture (TYH, CFC, YWC, SJC), pp. 597–602.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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