Travelled to:1 × France
1 × Germany
4 × USA
Collaborated with:C.Wu M.Hsieh S.Chen B.Ke J.Chen C.Lin C.Jiang S.Chang C.Wu K.Cheng C.Wang C.Wang S.Huang C.Lo M.Lee J.Yeh C.Li C.Lee S.Chang L.Denq C.Chi H.Hsu M.Chu J.Liou P.Huang H.Ma J.Bor C.Tien C.Wang Y.Kuo T.Chang
Talks about:design (3) test (3) platform (2) interfac (2) memori (2) multi (2) port (2) base (2) infrastructur (1) contactless (1)
Person: Chih-Tsun Huang
DBLP: Huang:Chih=Tsun
Contributed to:
201120082006
200620011997Wrote 7 papers:
- DAC-2011-ChenKCH #analysis #multi #reliability
- Reliability analysis and improvement for multi-level non-volatile memories with soft information (SLC, BRK, JNC, CTH), pp. 753–758.
- DAC-2011-LiLWCDCHCLHHMBWTWKHC #interface #low cost #testing
- A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing (CFL, CYL, CHW, SLC, LMD, CCC, HJH, MYC, JJL, SYH, PCH, HPM, JCB, CWW, CCT, CHW, YSK, CTH, TYC), pp. 771–776.
- DAC-2008-HsiehH #debugging #embedded #framework #interface #platform
- An embedded infrastructure of debug and trace interface for the DSP platform (MCH, CTH), pp. 866–871.
- DAC-2006-WangLLYHWH #design #framework #network #platform #security
- A network security processor design based on an integrated SOC design and test platform (CHW, CYL, MSL, JCY, CTH, CWW, SYH), pp. 490–495.
- DATE-DF-2006-LinHJC #optimisation #pattern matching #regular expression
- Optimization of regular expression pattern matching circuits on FPGA (CHL, CTH, CPJ, SCC), pp. 12–17.
- DAC-2001-WuHCWW #algorithm #generative #multi #scheduling
- Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories (CFW, CTH, KLC, CWW, CWW), pp. 301–306.
- EDTC-1997-HuangW #array #design #performance
- High-speed C-testable systolic array design for Galois-field inversion (CTH, CWW), pp. 342–346.