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Travelled to:
1 × Germany
2 × USA
Collaborated with:
Z.Hsu I.Chuang S.Huang C.Hsu J.Liao S.Fang C.Weng W.Hsieh C.Wang C.Lo M.Lee C.Huang C.Wu
Talks about:
design (3) power (3) platform (2) integr (2) base (2) architectur (1) methodolog (1) processor (1) abstract (1) virtual (1)

Person: Jen-Chieh Yeh

DBLP DBLP: Yeh:Jen=Chieh

Contributed to:

DAC 20112011
DATE 20102010
DAC 20062006

Wrote 3 papers:

DAC-2011-HsuLFWHHY #analysis #design #manycore #modelling #named
PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs (CWH, JLL, SCF, CCW, SYH, WTH, JCY), pp. 47–52.
DATE-2010-HsuYC #architecture #framework #refinement
An accurate system architecture refinement methodology with mixed abstraction-level virtual platform (ZMH, JCY, IYC), pp. 568–573.
DAC-2006-WangLLYHWH #design #framework #network #platform #security
A network security processor design based on an integrated SOC design and test platform (CHW, CYL, MSL, JCY, CTH, CWW, SYH), pp. 490–495.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.