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Travelled to:
11 × USA
3 × France
4 × Germany
Collaborated with:
M.Marek-Sadowska D.I.Cheng K.Cheng C.Lung K.Wu Y.Shi D.Chiou Y.Su M.Lee J.Chien R.Hsu H.Lin H.Chou W.Wen Y.Chen K.Lai C.Hsieh T.Tien T.Tsai D.Marculescu Y.Ho D.Kwai Y.Kao K.Tsai Z.Zeng C.Chou D.Juan Y.Chen D.Wang S.Chen C.Yeh C.Lin C.Huang C.Jiang C.Yeh M.Chang W.Jone N.S.Woo K.Yeh H.Yu S.Lin J.Chen J.Li S.Huang C.Lin K.Chen T.Wang W.Hon H.Lin C.Wang Y.Chen C.Huang Y.Yang C.Shen
Talks about:
effici (4) power (4) optim (4) synthesi (3) thermal (3) analysi (3) driven (3) design (3) algorithm (2) function (2)

Person: Shih-Chieh Chang

DBLP DBLP: Chang:Shih=Chieh

Contributed to:

DAC 20142014
DATE 20142014
DAC 20132013
DATE 20122012
DAC 20112011
DATE 20112011
DAC 20102010
DATE 20102010
DAC 20072007
DAC 20062006
DATE Designers’ Forum 20062006
DAC 20042004
DATE 20022002
DAC 19991999
DAC 19981998
DAC 19951995
DAC 19941994

Wrote 23 papers:

DAC-2014-ChenWLWSC #design #monitoring #scalability
Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs (YGC, TW, KYL, WYW, YS, SCC), p. 6.
DAC-2014-ChienHLYC #testing
Contactless Stacked-die Testing for Pre-bond Interposers (JHC, RSH, HJL, KYY, SCC), p. 6.
DATE-2014-ChenLLSHC #3d
Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits (YGC, KYL, MCL, YS, WKH, SCC), pp. 1–4.
DATE-2014-ChienYHLC #analysis #geometry #image
Package geometric aware thermal analysis by infrared-radiation thermal images (JHC, HY, RSH, HJL, SCC), pp. 1–4.
DAC-2013-LinCLWC #detection #fuzzy #novel
A novel fuzzy matching model for lithography hotspot detection (SYL, JYC, JCL, WYW, SCC), p. 6.
DATE-2012-LinWCCCHYS #analysis #functional #mutation testing #probability
A probabilistic analysis method for functional qualification under Mutation Analysis (HYL, CYW, SCC, YCC, HMC, CYH, YCY, CCS), pp. 147–152.
DATE-2012-WuLMC #approach #correlation
Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms (KCW, MCL, DM, SCC), pp. 1269–1274.
DAC-2011-LungSHSC #3d #fault tolerance #network
Fault-tolerant 3D clock network (CLL, YSS, SHH, YS, SCC), pp. 645–651.
DATE-2011-LungHKC #3d #manycore #online #optimisation #throughput
Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization (CLL, YLH, DMK, SCC), pp. 8–13.
DAC-2010-KaoCTC #detection #performance
An efficient phase detector connection structure for the skew synchronization system (YCK, HMC, KTT, SCC), pp. 729–734.
DATE-2010-LungZCC #optimisation
Clock skew optimization considering complicated power modes (CLL, ZYZ, CHC, SCC), pp. 1474–1479.
DAC-2007-ChiouJCC #algorithm #fine-grained #power management
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization (DSC, DCJ, YTC, SCC), pp. 81–86.
DAC-2007-SuWCM #design #optimisation #performance
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs (YSS, DCW, SCC, MMS), pp. 976–981.
DAC-2006-ChiouCCY #power management
Timing driven power gating (DSC, SHC, SCC, CY), pp. 121–124.
DATE-DF-2006-LinHJC #optimisation #pattern matching #regular expression
Optimization of regular expression pattern matching circuits on FPGA (CHL, CTH, CPJ, SCC), pp. 12–17.
Re-synthesis for delay variation tolerance (SCC, CTH, KCW), pp. 814–819.
Crosstalk Alleviation for Dynamic PLAs (TKT, TKT, SCC), pp. 683–687.
DAC-1999-YehCCJ #design
Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications (CWY, MCC, SCC, WBJ), pp. 68–71.
DAC-1998-ChangC #performance
Efficient Boolean Division and Substitution (SCC, DIC), pp. 342–347.
DAC-1995-ChangMC #algorithm #performance #set
An Efficient Algorithm for Local Don’t Care Sets Calculation (SCC, MMS, KTC), pp. 663–667.
DAC-1995-LinCCMC #logic #synthesis
Logic Synthesis for Engineering Change (CCL, KCC, SCC, MMS, KTC), pp. 647–652.
DAC-1994-ChangCWM #layout #logic #synthesis
Layout Driven Logic Synthesis for FPGAs (SCC, KTC, NSW, MMS), pp. 308–313.
EDAC-1994-ChangCM #multi
Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions (SCC, DIC, MMS), pp. 620–624.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.