BibSLEIGH corpus
BibSLEIGH tags
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BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
2 × France
Collaborated with:
M.E.Gómez P.López V.Selfa J.Sahuquillo J.Duato D.Ludovici D.Bertozzi R.Peñaranda P.Navarro D.B.Garzón A.Strano M.Favalli F.G.Villamón S.Medardoni G.N.Gaydadjiev
Talks about:
network (3) exploit (3) multiprogram (2) workload (2) topolog (2) perform (2) design (2) chip (2) interconnect (1) architectur (1)

Person: Crispín Gómez Requena

DBLP DBLP: Requena:Crisp=iacute=n_G=oacute=mez

Contributed to:

PDP 20152015
PDP 20142014
DATE 20112011
DATE 20092009
PDP 20082008

Wrote 7 papers:

PDP-2015-NavarroSSGR #design #locality #multi
Row Tables: Design Choices to Exploit Bank Locality in Multiprogram Workloads (PN, VS, JS, MEG, CGR), pp. 22–26.
PDP-2015-PenarandaRGL #adaptation #algorithm #named
XORAdap: A HoL-Blocking Aware Adaptive Routing Algorithm (RP, CGR, MEG, PL), pp. 48–52.
PDP-2015-SelfaSRG #metric #multi #performance
Methodologies and Performance Metrics to Evaluate Multiprogram Workloads (VS, JS, CGR, MEG), pp. 150–154.
PDP-2014-GarzonGGLD #fault tolerance #named #performance
FT-RUFT: A Performance and Fault-Tolerant Efficient Indirect Topology (DBG, CGR, MEG, PL, JD), pp. 405–409.
DATE-2011-StranoGLFGB #architecture #scalability #self
Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture (AS, CGR, DL, MF, MEG, DB), pp. 661–666.
DATE-2009-LudoviciVMRGLGB #constraints #design
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints (DL, FGV, SM, CGR, MEG, PL, GNG, DB), pp. 562–565.
PDP-2008-RequenaGLD #network
Exploiting Wiring Resources on Interconnection Network: Increasing Path Diversity (CGR, MEG, PL, JD), pp. 20–29.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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