BibSLEIGH corpus
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Travelled to:
2 × France
2 × USA
Collaborated with:
J.Duato E.Baydal C.G.Requena M.E.Gómez J.M.Martínez A.Robles R.Alcover L.Zúnica J.D.Marín J.Flich J.Ferrer R.Peñaranda M.P.Malumbres D.B.Garzón J.C.Martínez V.Lorente A.Valero J.Sahuquillo S.Petit R.Canal D.Ludovici F.G.Villamón S.Medardoni G.N.Gaydadjiev D.Bertozzi
Talks about:
network (7) mechan (4) effici (4) design (4) rout (4) wormhol (3) congest (3) adapt (3) interconnect (2) technolog (2)

Person: Pedro López

DBLP DBLP: L=oacute=pez:Pedro

Contributed to:

PDP 20152015
PDP 20142014
DATE 20132013
PDP 20102010
DATE 20092009
PDP 20082008
PDP 20072007
PDP 20032003
PDP 20022002
PDP 20012001
HPCA 19991999
PDP 19991999
HPCA 19981998
PDP 19961996
PDP 19941994

Wrote 16 papers:

PDP-2015-PenarandaRGL #adaptation #algorithm #named
XORAdap: A HoL-Blocking Aware Adaptive Routing Algorithm (RP, CGR, MEG, PL), pp. 48–52.
PDP-2014-GarzonGGLD #fault tolerance #named #performance
FT-RUFT: A Performance and Fault-Tolerant Efficient Indirect Topology (DBG, CGR, MEG, PL, JD), pp. 405–409.
DATE-2013-LorenteVSPCLD #power management #ram
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes (VL, AV, JS, SP, RC, PL, JD), pp. 83–88.
PDP-2010-FerrerBRLD #scalability
A Scalable and Early Congestion Management Mechanism for MINs (JLF, EB, AR, PL, JD), pp. 43–50.
DATE-2009-LudoviciVMRGLGB #constraints #design
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints (DL, FGV, SM, CGR, MEG, PL, GNG, DB), pp. 562–565.
PDP-2008-RequenaGLD #network
Exploiting Wiring Resources on Interconnection Network: Increasing Path Diversity (CGR, MEG, PL, JD), pp. 20–29.
Congestion Management in MINs through Marked and Validated Packets (JLF, EB, AR, PL, JD), pp. 254–261.
PDP-2003-MartinezFRLD #adaptation #network
Supporting Adaptive Routing in InfiniBand Networks (JCM, JF, AR, PL, JD), pp. 165–172.
PDP-2002-BaydalLD #adaptation #algorithm
Increasing the Adaptivity of Routing Algorithms for k-ary n-cubes (EB, PL, JD), pp. 455–462.
PDP-2002-FlichMLD #latency
Removing the Latency Overhead of the ITB Mechanism in COWs with Source Routing (JF, MPM, PL, JD), pp. 463–470.
PDP-2001-BaydalLD #network
A Congestion Control Mechanism for Wormhole Networks (EB, PL, JD), pp. 19–26.
HPCA-1999-MartinezLD #concurrent #detection #performance
Impact of Buffer Size on the Efficiency of Deadlock Detection (JMM, PL, JD), pp. 315–318.
PDP-1999-LopezADZ #design #network #optimisation #robust #throughput
Optimizing network throughput: optimal versus robust design (PL, RA, JD, LZ), pp. 45–52.
HPCA-1998-LopezMD #concurrent #detection #distributed #network #performance
A Very Efficient Distributed Deadlock Detection Mechanism for Wormhole Networks (PL, JMM, JD), pp. 57–66.
PDP-1996-AlcoverLDZ #analysis #design #interactive #network #statistics
Interconnection Network Design: A Statistical Analysis of Interactions between Factors (RA, PL, JD, LZ), pp. 211–218.
PDP-1994-MarinL #design #performance #requirements
Bandwidth Requirements For Wormhole Switches: A Simple And Efficient Design (JDM, PL), pp. 377–384.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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