BibSLEIGH — Davide

Travelled to:

1 × Italy
1 × USA
7 × France
7 × Germany

Collaborated with:

L.Benini S.Medardoni M.Milano A.Ghiribaldi G.D.Micheli D.Ludovici L.Ramini P.Grani S.Bartolini A.Strano M.Ruggiero F.Angiolini M.Balboni J.Flich S.M.Nowick G.Paci M.Lajolo G.N.Gaydadjiev F.Poletti C.G.Requena M.E.Gómez C.Zambelli M.Indaco S.D.Carlo P.Prinetto P.Olivo B.Stefano E.Macii S.Bertozzi A.Acquaviva A.Poggiali A.Raghunathan S.Ravi A.Guerri M.Loghi R.Zafalon H.T.Fankem M.Favalli G.Strano C.Pistritto S.Stergiou S.Carta L.Raffo J.L.Abellán J.F.Peinador M.E.Acacio D.Bortolotti A.Marongiu M.Fabiano F.G.Villamón P.López I.A.Khatib M.Bechara H.Khalifeh A.Jantsch R.Nabiev L.Zuolo R.Micheloni S.Galfano

Talks about:

chip (10) design (9) communic (5) system (5) architectur (4) network (4) explor (4) use (4) no (4) processor (3)

Person: Davide Bertozzi

DBLP: Bertozzi:Davide

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

Wrote 22 papers:

DATE-2015-BalboniFB #configuration management #distributed #latency #multi #network #scalability #using: Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration (MB, JF, DB), pp. 806–811.
DATE-2014-RaminiGGBFB #architecture #energy: Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline (LR, AG, PG, SB, HTF, DB), pp. 1–6.
DATE-2014-ZuoloZMGICPOB #design #fine-grained #framework #named: SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives (LZ, CZ, RM, SG, MI, SDC, PP, PO, DB), pp. 1–6.
DATE-2013-GhiribaldiBN #architecture #effectiveness #manycore: A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems (AG, DB, SMN), pp. 332–337.
DATE-2013-RaminiGBB #3d #analysis #manycore #power management #using: Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis (LR, PG, SB, DB), pp. 1589–1594.
DATE-2012-AbellanPABBMB #clustering #communication #design #framework: Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs (JLA, JFP, MEA, DB, DB, AM, LB), pp. 491–496.
DATE-2012-ZambelliIFCPOB #approach #trade-off: A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories (CZ, MI, MF, SDC, PP, PO, DB), pp. 881–886.
DATE-2011-StranoGLFGB #architecture #scalability #self: Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture (AS, CGR, DL, MF, MEG, DB), pp. 661–666.
DATE-2010-LudoviciSGBB #design #effectiveness #flexibility: Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs (DL, AS, GNG, LB, DB), pp. 679–684.
DATE-2009-LudoviciVMRGLGB #constraints #design: Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints (DL, FGV, SM, CGR, MEG, PL, GNG, DB), pp. 562–565.
DATE-2009-PaciBB #adaptation #bias #communication #effectiveness #variability: Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels (GP, DB, LB), pp. 1404–1409.
DATE-2008-MedardoniLB #design #self: Variation tolerant NoC design by means of self-calibrating links (SM, ML, DB), pp. 1402–1407.
DATE-2008-StefanoBBM #design #multi #pipes and filters #process: Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style (BS, DB, LB, EM), pp. 967–972.
ICLP-2008-BeniniBM #constraints #multi #platform #policy #programming #resource management #using: Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming (LB, DB, MM), pp. 470–484.
DATE-2007-MedardoniRBBSP #communication #in memory #industrial #interactive #memory management #platform: Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms (SM, MR, DB, LB, GS, CP), pp. 660–665.
DAC-2006-KhatibPBBBKJN #analysis #architecture #design #monitoring #multi #realtime: A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration (IAK, FP, DB, LB, MB, HK, AJ, RN), pp. 125–130.
DATE-2006-BertozziABP #migration #multi: Supporting task migration in multi-processor systems-on-chip: a feasibility study (SB, AA, DB, AP), pp. 15–20.
DATE-2006-RuggieroGBPM #framework #multi #scheduling: Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip (MR, AG, DB, FP, MM), pp. 3–8.
DATE-2005-StergiouACRBM #abstract syntax tree #design #library #network #pipes and filters #synthesis: ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips (SS, FA, SC, LR, DB, GDM), pp. 1188–1193.
DATE-v2-2004-LoghiABBZ #communication: Analyzing On-Chip Communication in a MPSoC Environment (ML, FA, DB, LB, RZ), pp. 752–757.
DATE-2003-BertozziRBR #embedded #energy #optimisation #performance #protocol: Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems (DB, AR, LB, SR), pp. 10706–10713.
DATE-2002-BertozziBM #encoding #fault #power management: Low Power Error Resilient Encoding for On-Chip Data Buses (DB, LB, GDM), pp. 102–109.