BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × Germany
2 × France
3 × USA
Collaborated with:
L.Yu D.A.Antoniadis I.M.Elfadel S.Saxena C.Hess L.Wei I.A.M.Elfadel V.Mehrotra S.L.Sam A.Chandrakasan R.Vallishayee S.R.Nassif G.R.Chin W.C.D.Jr. A.S.Wong A.R.Neureuther R.W.Dutton
Talks about:
model (4) statist (2) perform (2) estim (2) use (2) interconnect (1) transistor (1) posteriori (1) methodolog (1) technolog (1)

Person: Duane S. Boning

DBLP DBLP: Boning:Duane_S=

Contributed to:

DATE 20152015
DAC 20142014
DATE 20142014
DATE 20132013
DAC 20002000
DAC 19911991

Wrote 6 papers:

DATE-2015-YuSHEAB #library #multi #statistics #using
Statistical library characterization using belief propagation across multiple technology nodes (LY, SS, CH, IME, DAA, DSB), pp. 1383–1388.
DAC-2014-YuSHEAB #metric #parametricity #using
Remembrance of Transistors Past: Compact Model Parameter Extraction Using Bayesian Inference and Incomplete New Measurements (LY, SS, CH, IAME, DAA, DSB), p. 6.
DATE-2014-YuSHEAB #estimation #performance #physics
Efficient performance estimation with very small sample size via physical subspace projection and maximum a posteriori estimation (LY, SS, CH, IME, DAA, DSB), pp. 1–6.
DATE-2013-YuWAEB #modelling #statistics
Statistical modeling with the virtual source MOSFET model (LY, LW, DAA, IME, DSB), pp. 1454–1457.
DAC-2000-MehrotraSBCVN #modelling #performance
A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance (VM, SLS, DSB, AC, RV, SRN), pp. 172–175.
Linking TCAD to EDA — Benefits and Issues (GRC, WCDJ, DSB, ASW, ARN, RWD), pp. 573–578.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.