BibSLEIGH — Anantha

Travelled to:

3 × Germany
8 × USA

Collaborated with:

J.Kao D.Antoniadis A.Sinha G.Konduri J.Goodman A.P.Dancy S.Narendra T.Xanthopoulos Y.Yaoi M.Potkonjak M.B.Srivastava I.Yang C.Vieri M.Qazi M.Tikekar L.Dolecek D.Shah B.Bougard F.Catthoor D.C.Daly W.Dehaene S.Park T.Krishna C.O.Chen B.K.Daya L.Peh R.Blázquez F.S.Lee D.D.Wentzloff B.P.Ginsburg J.Powell V.Mehrotra S.L.Sam D.S.Boning R.Vallishayee S.R.Nassif R.Rithe J.Gu A.Wang S.Datla G.Gammie D.Buss T.Basten L.Benini M.Lindwer J.Liu R.Min F.Zhao

Talks about:

design (4) base (4) effici (3) model (3) tool (3) architectur (2) multipl (2) analysi (2) voltag (2) variat (2)

Person: Anantha Chandrakasan

DBLP: Chandrakasan:Anantha

Contributed to:

2012

2010

2005

2003

2001

2000

1999

1998

1997

1996

1994

Wrote 15 papers:

DAC-2012-ParkKCDCP #prototype: Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI (SP, TK, CHOC, BKD, AC, LSP), pp. 398–405.
DATE-2010-QaziTDSC #analysis #performance #reduction: Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis (MQ, MT, LD, DS, AC), pp. 801–806.
DATE-2010-RitheGWDGBC #analysis #logic #statistics: Non-linear Operating Point Statistical Analysis for Local Variations in logic timing at low voltage (RR, JG, AW, SD, GG, DB, AC), pp. 965–968.
DATE-2005-BlazquezLWGPC #architecture: Direct Conversion Pulsed UWB Transceiver Architecture (RB, FSL, DDW, BPG, JP, AC), pp. 94–95.
DATE-2005-BougardCDCD #energy #modelling #network #performance #standard: Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives (BB, FC, DCD, AC, WD), pp. 196–201.
DATE-2003-BastenBCLLMZ #scalability: Scaling into Ambient Intelligence (TB, LB, AC, ML, JL, RM, FZ), pp. 10076–10083.
DAC-2001-SinhaC #energy #named #profiling #web: JouleTrack — A Web Based Tool for Software Energy Profiling (AS, AC), pp. 220–225.
DAC-2000-MehrotraSBCVN #modelling #performance: A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance (VM, SLS, DSB, AC, RV, SRN), pp. 172–175.
DAC-1999-GoodmanCD #design #embedded #encryption #implementation #scalability: Design and Implementation of a Scalable Encryption Processor with Embedded Variable DC/DC Converter (JG, AC, APD), pp. 855–860.
DAC-1999-KonduriC #collaboration #design #distributed #framework: A Framework for Collaborative and Distributed Web-Based Design (GK, AC), pp. 898–903.
DAC-1998-KaoNC: MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns (JK, SN, AC), pp. 495–500.
DAC-1997-KaoCA #multi: Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology (JK, AC, DA), pp. 409–414.
DAC-1997-XanthopoulosYC #architecture #case study #estimation #using: Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT (TX, YY, AC), pp. 415–420.
DAC-1996-ChandrakasanYVA #design #tool support: Design Considerations and Tools for Low-voltage Digital System Design (AC, IY, CV, DA), pp. 113–118.
DAC-1994-PotkonjakSC #constant #multi #performance #using: Efficient Substitution of Multiple Constant Multiplications by Shifts and Additions Using Iterative Pairwise Matching (MP, MBS, AC), pp. 189–194.