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Travelled to:
1 × France
2 × USA
Collaborated with:
R.Aitken D.Flynn S.Sinha V.Chandra B.Cline Y.Cao S.Venkataraman R.Puri S.Griffith A.Oberai R.Madge W.Ng Y.Zorian
Talks about:
model (2) manufactur (1) technolog (1) parametr (1) silicon (1) predict (1) improv (1) explor (1) design (1) correl (1)

Person: Greg Yeric

DBLP DBLP: Yeric:Greg

Contributed to:

DAC 20122012
DATE 20112011
DAC 20072007

Wrote 3 papers:

DAC-2012-SinhaYCCC #design #modelling #predict
Exploring sub-20nm FinFET design with predictive technology models (SS, GY, VC, BC, YC), pp. 283–288.
DATE-2011-AitkenYF #correlation #modelling #parametricity
Correlating models and silicon for improved parametric yield (RA, GY, DF), pp. 1159–1163.
DAC-2007-VenkataramanPGOMYNZ
Making Manufacturing Work For You (SV, RP, SG, AO, RM, GY, WN, YZ), pp. 107–108.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.