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Travelled to:
1 × Germany
2 × USA
Collaborated with:
D.Blaauw S.Sinha G.Yeric V.Chandra Y.Cao V.Joshi D.Sylvester K.Agarwal K.Chopra A.Torres S.Sundareswaran
Talks about:
model (2) transistor (1) technolog (1) predict (1) stress (1) specif (1) reduct (1) leakag (1) layout (1) explor (1)

Person: Brian Cline

DBLP DBLP: Cline:Brian

Contributed to:

DAC 20122012
DAC 20082008
DATE 20082008

Wrote 3 papers:

DAC-2012-SinhaYCCC #design #modelling #predict
Exploring sub-20nm FinFET design with predictive technology models (SS, GY, VC, BC, YC), pp. 283–288.
DAC-2008-JoshiCSBA #power management #reduction #using
Leakage power reduction using stress-enhanced layouts (VJ, BC, DS, DB, KA), pp. 912–917.
DATE-2008-ClineCBTS #modelling
Transistor-Specific Delay Modeling for SSTA (BC, KC, DB, AT, SS), pp. 592–597.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.