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Travelled to:
2 × USA
5 × Germany
Collaborated with:
R.Dömer H.Tabkhi J.Zhang N.Teimouri Y.Hwang S.Abdi D.D.Gajski R.Ubal D.Schaa P.Mistry X.Gong Y.Ukidave Z.Chen D.R.Kaeli
Talks about:
model (5) transact (2) specif (2) explor (2) design (2) space (2) level (2) rtos (2) preemptiv (1) heterogen (1)

Person: Gunar Schirner

DBLP DBLP: Schirner:Gunar

Contributed to:

DAC 20152015
DAC 20142014
DATE 20142014
DATE 20122012
DATE 20102010
DATE 20082008
DATE 20062006

Wrote 7 papers:

DAC-2015-TeimouriTS #challenge
Revisiting accelerator-rich CMPs: challenges and solutions (NT, HT, GS), p. 6.
DAC-2014-UbalSMGUCSK #design #performance #reliability
Exploring the Heterogeneous Design Space for both Performance and Reliability (RU, DS, PM, XG, YU, ZC, GS, DRK), p. 6.
DATE-2014-ZhangS #automation #design #specification
Automatic specification granularity tuning for design space exploration (JZ, GS), pp. 1–6.
DATE-2012-TabkhiS #approach #power management
Application-specific power-efficient approach for reducing register file vulnerability (HT, GS), pp. 574–577.
DATE-2010-HwangSAG #modelling #transaction
Accurate timed RTOS model for transaction level modeling (YH, GS, SA, DDG), pp. 1333–1336.
DATE-2008-SchirnerD #modelling #scheduling #using
Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling (GS, RD), pp. 122–127.
DATE-2006-SchirnerD #analysis #modelling #transaction
Quantitative analysis of transaction level models for the AMBA bus (GS, RD), pp. 230–235.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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