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Travelled to:
2 × USA
Collaborated with:
S.D.Posluszny N.Aoki D.Boerstler P.K.Coulman S.H.Dhong B.K.Flachs N.Kojima O.Kwon K.Lee D.Meltzer K.J.Nowka J.Park J.Peter J.Silberman O.Takahashi P.Villarrubia
Talks about:
processor (2) design (2) microprocessor (1) architectur (1) methodolog (1) frequenc (1) effici (1) closur (1) power (1) time (1)

Person: H. Peter Hofstee

DBLP DBLP: Hofstee:H=_Peter

Contributed to:

HPCA 20052005
DAC 20002000

Wrote 2 papers:

HPCA-2005-Hofstee #architecture #performance
Power Efficient Processor Architecture and The Cell Processor (HPH), pp. 258–262.
DAC-2000-PoslusznyABCDFHKKLMNPPSTV #design
“Timing closure by design”, a high frequency microprocessor design methodology (SDP, NA, DB, PKC, SHD, BKF, HPH, NK, OK, KL, DM, KJN, JP, JP, JS, OT, PV), pp. 712–717.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.