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Travelled to:
1 × Spain
3 × France
3 × USA
Collaborated with:
M.Arjomand M.Modarressi M.Asadinia A.Tavakkol S.Hessabi M.H.Farahabady M.Monemizadeh M.Ould-Khaoua M.Ghane N.Teimouri A.Habibi R.Moraveji A.Y.Zomaya A.Mirhosseini M.Sadrosadati M.H.Samavatian H.Abbasitabar P.K.Hamedani N.D.E.Jerger A.E.Kiasari D.Rahmati A.Fakhrzadehgan Seyed Borna Ehsani Mario Drumond B.Falsafi R.Ausavarungnirun O.Mutlu
Talks about:
network (10) chip (8) effici (4) multiprocessor (3) base (3) interconnect (2) architectur (2) hypercub (2) virtual (2) perform (2)

Person: Hamid Sarbazi-Azad

DBLP DBLP: Sarbazi-Azad:Hamid

Contributed to:

DATE 20152015
DAC 20142014
PDP 20142014
PDP 20132013
PDP 20122012
DATE 20112011
PDP 20112011
DAC 20102010
DATE 20092009
PDP 20092009
PDP 20082008
SAC 20052005
SAC 20022002
ASPLOS 20182018

Wrote 16 papers:

DATE-2015-MirhosseiniSFMS #energy #network
An energy-efficient virtual channel power-gating mechanism for on-chip networks (AM, MS, AF, MM, HSA), pp. 1527–1532.
DAC-2014-AsadiniaAS #named #on-demand
OD3P: On-Demand Page Paired PCM (MA, MA, HSA), p. 6.
DAC-2014-SamavatianAAS #architecture #performance
An Efficient STT-RAM Last Level Cache Architecture for GPUs (MHS, HA, MA, HSA), p. 6.
PDP-2014-GhaneAS #multi #predict
An Opto-electrical NoC with Traffic Flow Prediction in Chip Multiprocessors (MG, MA, HSA), pp. 440–443.
PDP-2013-TeimouriMS #performance
Power and Performance Efficient Partial Circuits in Packet-Switched Networks-on-Chip (NT, MM, HSA), pp. 509–513.
PDP-2012-HamedaniHSJ #3d #constraints #network
Exploration of Temperature Constraints for Thermal Aware Mapping of 3D Networks on Chip (PKH, SH, HSA, NDEJ), pp. 499–506.
DATE-2011-AsadiniaMTS #using
Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point links (MA, MM, AT, HSA), pp. 413–418.
PDP-2011-HabibiAS #algorithm #multi #network
Multicast-Aware Mapping Algorithm for On-chip Networks (AH, MA, HSA), pp. 455–462.
DAC-2010-ModarressiST #architecture #configuration management #network #performance
An efficient dynamically reconfigurable on-chip network architecture (MM, HSA, AT), pp. 166–169.
DATE-2009-ModarressiSA #hybrid #network
A hybrid packet-circuit switched on-chip network based on SDM (MM, HSA, MA), pp. 566–569.
PDP-2009-MoravejiSZ #network
A General Methodology for Routing in Irregular Networks (RM, HSA, AYZ), pp. 155–160.
PDP-2008-KiasariRSH #markov #performance
A Markovian Performance Model for Networks-on-Chip (AEK, DR, HSA, SH), pp. 157–164.
SAC-2005-FarahabadyS #multi #network #recursion
The recursive transpose-connected cycles (RTCC) interconnection network for multiprocessors (MHF, HSA), pp. 734–738.
SAC-2005-MonemizadehS #multi #network #scalability
The necklace-hypercube: a well scalable hypercube-based interconnection network for multiprocessors (MM, HSA), pp. 729–733.
SAC-2002-Sarbazi-AzadO #adaptation
A simple mathematical model of adaptive routing in wormhole k-ary n-cubes (HSA, MOK), pp. 835–839.
ASPLOS-2018-SadrosadatiMESD #hardware #named
LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching (MS, AM, SBE, HSA, MD, BF, RA, OM), pp. 489–502.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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