Travelled to:1 × France
1 × Germany
Collaborated with:B.Cheon E.Lee L.Wang X.Wen P.Hsu J.Park H.Chao S.Wu G.Eneman V.Moroz D.Milojevic M.Choi K.D.Meyer A.Mercha E.Beyne T.Hoffmann G.V.d.Plas
Talks about:configur (1) silicon (1) multipl (1) compact (1) stress (1) analyt (1) speed (1) model (1) logic (1) estim (1)
Person: J. Cho
DBLP: Cho:J=
Contributed to:
20112005Wrote 2 papers:
- DATE-2011-EnemanCMMCMMBHP #estimation #multi
- An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations (GE, JC, VM, DM, MC, KDM, AM, EB, TH, GVdP), pp. 505–506.
- DATE-2005-CheonLWWHCPCW #logic
- At-Speed Logic BIST for IP Cores (BC, EL, LTW, XW, PH, JC, JP, HC, SW), pp. 860–861.