BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × Korea
1 × Taiwan
2 × Portugal
Collaborated with:
S.Dauzère-Pérès G.Rodríguez-Verján S.Housseman S.Bouzid C.Cauvet C.S.Frydman P.Viale N.Benayadi M.L.Goc E.Tartiere A.Thieullen Taki Eddine Korabi Guillaume Graton El Mostafa El Adel Mustapha Ouladsine
Talks about:
process (4) semiconductor (3) manufactur (3) microelectron (2) approach (2) inform (2) applic (2) wafer (2) sampl (2) model (2)

Person: Jacques Pinaton

DBLP DBLP: Pinaton:Jacques

Contributed to:

CASE 20142014
ICEIS v1 20142014
CASE 20122012
ICEIS AIDSS 20102010
CASE 20192019

Wrote 5 papers:

CASE-2014-HoussemanDRP #reduction
Smart dynamic sampling for wafer at risk reduction in semiconductor manufacturing (SH, SDP, GRV, JP), pp. 780–785.
ICEIS-v1-2014-BouzidCFP #approach #enterprise #retrieval #semantics
A Pattern-based Approach for Semantic Retrieval of Information Resources in Enterprises — Application Within STMicroelectronics (SB, CC, CSF, JP), pp. 193–200.
Dispatching of lots to dynamically reduce the wafers at risk in semiconductor manufacturing (GRV, ET, JP, SDP, AT), pp. 920–923.
ICEIS-AIDSS-2010-VialeBGP #approach #modelling #process #scalability #sequence #using
Modeling Large Scale Manufacturing Process from Timed Data — Using the TOM4L Approach and Sequence Alignment Information for Modeling STMicroelectronics’ Production Processes (PV, NB, MLG, JP), pp. 129–138.
CASE-2019-KorabiGAOP #monitoring #process
Monitoring of a sampled process data under Run-to-Run control: application to a semiconductor process (TEK, GG, EMEA, MO, JP), pp. 930–935.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.