BibSLEIGH
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Used together with:
semiconductor (12)
cluster (11)
schedul (10)
tool (10)
fabric (9)

Stem wafer$ (all stems)

35 papers:

CASECASE-2015-PanZQ #clustering #how #process #tool support
How to start-up dual-arm cluster tools involving a wafer revisiting process (CP, MZ, YQ), pp. 1194–1199.
CASECASE-2015-YuWZT #design
Controller design and optimal tuning of a wafer handling robot (XY, CW, YZ, MT), pp. 640–646.
CASECASE-2015-ZhuQZ #clustering #modelling #multi #petri net #scheduling #tool support
Petri net modeling and one-wafer scheduling of single-arm tree-like multi-cluster tools (QZ, YQ, MZ), pp. 292–297.
MoDELSMoDELS-2015-SandenRGBJVS #composition #design #modelling
Modular model-based supervisory controller design for wafer logistics in lithography machines (BvdS, MAR, MG, TB, JJ, JV, RRHS), pp. 416–425.
CASECASE-2014-HoussemanDRP #reduction
Smart dynamic sampling for wafer at risk reduction in semiconductor manufacturing (SH, SDP, GRV, JP), pp. 780–785.
CASECASE-2013-GrosbardKTR #composition #network #using
A queuing network model for wafer fabrication using decomposition without aggregation (DG, AK, IT, GR), pp. 717–722.
CASECASE-2013-JinM #algorithm #clustering #constraints #scheduling #tool support
Transient scheduling of single armed cluster tools: Algorithms for wafer residency constraints (HYJ, JRM), pp. 856–861.
CASECASE-2013-LiX #adaptation #learning
Off-line learning based adaptive dispatching rule for semiconductor wafer fabrication facility (LL, HX), pp. 1028–1033.
CASECASE-2013-QiaoWZ #clustering #scheduling #tool support
Scheduling of time constrained dual-arm cluster tools with wafer revisiting (YQ, NW, MZ), pp. 868–873.
CASECASE-2013-ZhuWQZ #clustering #modelling #multi #petri net #scheduling #tool support
Petri net modeling and one-wafer scheduling of single-arm multi-cluster tools (QZ, NW, YQ, MZ), pp. 862–867.
DACDAC-2013-ZhangLSSR #automation #clustering
Automatic clustering of wafer spatial signatures (WZ, XL, SS, AJS, RAR), p. 6.
DATEDATE-2013-GaoBW #paradigm #performance
A new paradigm for trading off yield, area and performance to enhance performance per wafer (YG, MAB, YW), pp. 1753–1758.
DATEDATE-2013-HuangKCM #correlation #modelling #testing
Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests (KH, NK, JMCJ, YM), pp. 553–558.
CASECASE-2012-LiJJ #policy
A pull VPLs based release policy and dispatching rule for semiconductor wafer fabrication (YL, ZJ, WJ), pp. 396–400.
CASECASE-2012-LiLS #constraints #process
Dispatching rule considering time-constraints on processes for semiconductor wafer fabrication facility (LL, YFL, ZJS), pp. 407–412.
CASECASE-2012-QiaoWZ #analysis #clustering #petri net #scheduling #tool support
Petri net-based scheduling analysis of dual-arm cluster tools with wafer revisiting (YQ, NW, MZ), pp. 206–211.
CASECASE-2012-Rodriguez-VerjanTPDT
Dispatching of lots to dynamically reduce the wafers at risk in semiconductor manufacturing (GRV, ET, JP, SDP, AT), pp. 920–923.
CASECASE-2012-YumKK #analysis #bibliography #perspective
Analysis of defective patterns on wafers in semiconductor manufacturing: A bibliographical review (BJY, JHK, SJK), pp. 86–90.
CASECASE-2011-LeeL #clustering #concurrent #multi
Concurrent processing of multiple wafer types in a single-armed cluster tool (JHL, TEL), pp. 102–107.
CASECASE-2011-QiaoWZ #analysis #clustering #modelling #tool support
Modeling and analysis of dual-arm cluster tools for wafer fabrication with revisiting (YQ, NW, MZ), pp. 90–95.
DATEDATE-2011-DrmanacSWWA #multi #optimisation #parametricity #predict #testing
Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits (DGD, NS, LW, LCW, MSA), pp. 794–799.
CASECASE-2010-BeyelerMN #automation #testing
Wafer-level inspection system for the automated testing of comb drive based MEMS sensors and actuators (FB, SM, BJN), pp. 698–703.
CASECASE-2009-WuCCZ #approach #clustering #novel #scheduling #tool support
A novel approach to scheduling of single-arm cluster tools with wafer revisiting (NW, FC, CC, MZ), pp. 567–572.
DACDAC-2009-ChengGSQH #modelling #variability
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability (LC, PG, CJS, KQ, LH), pp. 104–109.
CASECASE-2008-Morrison #evolution
Flow lines with regular service times: Evolution of delay, state dependent failures and semiconductor wafer fabrication (JRM), pp. 247–252.
DATEDATE-2008-BahukudumbiCK #scheduling
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs (SB, KC, RK), pp. 1103–1106.
CASECASE-2007-GengJ #capacity #nondeterminism
Capacity Planning for Semiconductor Wafer Fabrication with Uncertain Demand and Capacity (NG, ZJ), pp. 100–105.
CASECASE-2007-HuangLF #scheduling
Lot Dispatching and Scheduling Integrating OHT Traffic Information in the 300mm Wafer Fab (HWH, CHL, LCF), pp. 495–500.
CASECASE-2007-MorrisonM #clustering #on the #throughput #tool support
On the Throughput of Clustered Photolithography Tools: Wafer Advancement and Intrinsic Equipment Loss (JRM, MKM), pp. 88–93.
CASECASE-2007-ZhangG #approach
Calibration of Wafer Handling Robots: A Fixturing Approach (MTZ, KG), pp. 255–260.
CASECASE-2007-ZhangJ0 #multi #scheduling
Multi-criteria Dynamic Scheduling Methodology for Controlling a Semiconductor Wafer Fabrication System (HZ, ZJ, HH), pp. 213–218.
CASECASE-2006-WangQW #multi #optimisation #scheduling
Scheduling Semiconductor Wafer Fabrication with Optimization of Multiple objectives (ZW, FQ, QW), pp. 253–258.
DATEDATE-2006-NelsonZDBPMB #fault
Extraction of defect density and size distributions from wafer sort test results (JEN, TZ, RD, JGB, NP, WM, RD(B), pp. 913–918.
CASECASE-2005-ChangLJ #detection #fault #network #using
Using a two-layer competitive Hopfield neural network for semiconductor wafer defect detection (CYC, SYL, MJ), pp. 301–306.
DACDAC-1991-WalkerKS #database #editing #process #representation #statistics
A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator (DMHW, CSK, AJS), pp. 579–584.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.