Travelled to:1 × USA
3 × France
3 × Germany
Collaborated with:S.Guilley M.Nassar L.Sauvage O.Meynard F.Flament S.Bhasin Y.Souissi G.Duc Y.Mathieu S.Chaudhuri P.Hoogvorst S.Hamdioui G.D.Natale F.Smailbegovic G.v.Battum M.Tehranipoor D.Réal N.Homma X.T.Ngo I.Exurville Z.Najm J.Rigaud B.Robisson
Talks about:fpga (3) hardwar (2) attack (2) base (2) cryptoprocessor (1) electromagnet (1) countermeasur (1) precharacter (1) reconfigur (1) constraint (1)
Person: Jean-Luc Danger
DBLP: Danger:Jean=Luc
Contributed to:
201520142012201120102009
2008Wrote 8 papers:
- DATE-2015-NgoEBDGNRR #detection #hardware #metric
- Hardware trojan detection by delay and electromagnetic measurements (XTN, IE, SB, JLD, SG, ZN, JBR, BR), pp. 782–787.
- DATE-2014-HamdiouiDNSBT #hardware
- Hacking and protecting IC hardware (SH, JLD, GDN, FS, GvB, MT), pp. 1–7.
- DATE-2012-NassarSGD #named #performance
- RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs (MN, YS, SG, JLD), pp. 1173–1178.
- DATE-2011-MeynardRFGHD
- Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques (OM, DR, FF, SG, NH, JLD), pp. 1004–1009.
- DATE-2010-MeynardGDS
- Far Correlation-based EMA with a precharacterized leakage model (OM, SG, JLD, LS), pp. 977–980.
- DATE-2010-NassarBDDG #evaluation #named
- BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation (MN, SB, JLD, GD, SG), pp. 849–854.
- DATE-2009-SauvageGDMN #constraints
- Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints (LS, SG, JLD, YM, MN), pp. 640–645.
- DAC-2008-ChaudhuriGFHD #configuration management #embedded #runtime
- An 8x8 run-time reconfigurable FPGA embedded in a SoC (SC, SG, FF, PH, JLD), pp. 120–125.