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Travelled to:
3 × France
5 × Germany
Collaborated with:
N.Z.Haron A.J.v.d.Goor Z.Al-Ars M.Taouil Seyab G.D.Natale G.Gaydadjiev M.Cortez G.Roelofs M.Masadeh E.J.Marinissen G.Mueller F.Catthoor J.Danger F.Smailbegovic G.v.Battum M.Tehranipoor M.Nicolaidis D.Gizopoulos A.Grasset G.Groeseneken P.Bonnot M.Lefter G.R.Voicu M.Enachescu S.D.Cotofana S.Khan I.Agbo H.Kukner B.Kaczer P.Raghavan L.Xie H.A.D.Nguyen K.Bertels H.Corporaal H.Jiao D.Wouters L.Eike J.v.Lunteren
Talks about:
memori (5) test (5) base (4) fault (3) temperatur (2) framework (2) analysi (2) model (2) dram (2) nanoelectron (1)

Person: Said Hamdioui

DBLP DBLP: Hamdioui:Said

Contributed to:

DATE 20152015
DATE 20142014
DATE 20132013
DATE 20122012
DATE 20112011
DATE 20102010
DATE 20062006
DATE 20052005

Wrote 13 papers:

DATE-2015-HamdiouiXNTBCJC #architecture #data-driven #in memory
Memristor based computation-in-memory architecture for data-intensive applications (SH, LX, HADN, MT, KB, HC, HJ, FC, DW, LE, JvL), pp. 1718–1725.
DATE-2014-CortezRHN #testing
Testing PUF-based secure key storage circuits (MC, GR, SH, GDN), pp. 1–6.
DATE-2014-HamdiouiDNSBT #hardware
Hacking and protecting IC hardware (SH, JLD, GDN, FS, GvB, MT), pp. 1–7.
DATE-2014-KhanAHKKRC #analysis #bias
Bias Temperature Instability analysis of FinFET based SRAM cells (SK, IA, SH, HK, BK, PR, FC), pp. 1–6.
DATE-2014-TaouilMHM #3d
Interconnect test for 3D stacked memory-on-logic (MT, MM, SH, EJM), pp. 1–6.
DATE-2013-HamdiouiNGGGB #challenge #realtime #reliability
Reliability challenges of real-time systems in forthcoming technology nodes (SH, MN, DG, AG, GG, PB), pp. 129–134.
DATE-2013-LefterVTEHC #3d #integration #memory management #question
Is TSV-based 3D integration suitable for inter-die memory repair? (ML, GRV, MT, ME, SH, SDC), pp. 1251–1254.
DATE-2012-HaronH #fault
DfT schemes for resistive open defects in RRAMs (NZH, SH), pp. 799–804.
DATE-2011-HaronH #fault tolerance #hybrid #low cost
Cost-efficient fault-tolerant decoder for hybrid nanoelectronic memories (NZH, SH), pp. 265–268.
DATE-2010-GoorGH #memory management #testing
Memory testing with a RISC microcontroller (AJvdG, GG, SH), pp. 214–219.
DATE-2010-SeyabH #framework #modelling
NBTI modeling in the framework of temperature variation (S, SH), pp. 283–286.
DATE-2006-Al-ArsHG #fault #modelling #testing
Space of DRAM fault models and corresponding testing (ZAA, SH, AJvdG), pp. 1252–1257.
DATE-2005-Al-ArsHMG #analysis #fault #framework #generative #testing
Framework for Fault Analysis and Test Generation in DRAMs (ZAA, SH, GM, AJvdG), pp. 1020–1021.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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