Travelled to:1 × France
1 × Germany
2 × USA
Collaborated with:B.Akesson K.Goossens C.Weis N.Wehn S.Goossens M.Koedam
Talks about:power (3) time (3) dram (3) system (2) level (2) run (2) strategi (1) approach (1) process (1) perform (1)
Person: Karthik Chandrasekar
DBLP: Chandrasekar:Karthik
Contributed to:
2014
201320132012Wrote 4 papers:
- DATE-2014-0001GWKAWG #optimisation #performance #runtime
- Exploiting expendable process-margins in DRAMs for run-time performance optimization (KC, SG, CW, MK, BA, NW, KG), pp. 1–6.
- DAC-2013-0001WAWG #approach #empirical #estimation #towards
- Towards variation-aware system-level power estimation of DRAMs: an empirical approach (KC, CW, BA, NW, KG), p. 8.
- DATE-2013-0001WAWG #3d #energy #modelling
- System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs (KC, CW, BA, NW, KG), pp. 236–241.
- DAC-2012-0001AG #memory management #realtime #runtime
- Run-time power-down strategies for real-time SDRAM memory controllers (KC, BA, KG), pp. 988–993.