BibSLEIGH — Kees

Travelled to:

1 × Portugal
3 × USA
4 × France
5 × Germany

Collaborated with:

B.Akesson A.Hansson K.Chandrasekar M.D.Gomony A.B.Nejad C.Weis N.Wehn S.Goossens A.M.Molnos B.Vermeulen M.Coenen A.Radulescu M.Koedam M.E.Martinez T.Schenkelaars M.Subburaman P.Huang O.Moreira T.Kouters R.A.Stefan J.A.Ambrose J.W.v.d.Brand C.Ciordas T.Basten A.Nelson S.Murali G.D.Micheli F.Steenhof H.Duque B.Nilsson R.P.Llopis J.Dielissen O.P.Gangwal S.G.Pestana E.Rijpkema

Talks about:

time (10) network (9) chip (8) control (7) system (7) real (7) memori (5) dram (5) optim (4) architectur (3)

Person: Kees Goossens

DBLP: Goossens:Kees

Contributed to:

2014

2013

2012

2011

2010

2009

2007

2006

2005

Wrote 23 papers:

DATE-2014-0001GWKAWG #optimisation #performance #runtime: Exploiting expendable process-margins in DRAMs for run-time performance optimization (KC, SG, CW, MK, BA, NW, KG), pp. 1–6.
DATE-2014-GomonyAG #optimisation #performance #realtime: Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems (MDG, BA, KG), pp. 1–6.
DATE-2014-NelsonNMKG #composition #kernel #named #predict #realtime: CoMik: A predictable and cycle-accurately composable real-time microkernel (AN, ABN, AMM, MK, KG), pp. 1–4.
DAC-2013-0001WAWG #approach #empirical #estimation #towards: Towards variation-aware system-level power estimation of DRAMs: an empirical approach (KC, CW, BA, NW, KG), p. 8.
DATE-2013-0001WAWG #3d #energy #modelling: System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs (KC, CW, BA, NW, KG), pp. 236–241.
DATE-2013-GomonyAG #architecture #memory management #multi #realtime: Architecture and optimal configuration of a real-time multi-channel memory controller (MDG, BA, KG), pp. 1307–1312.
DATE-2013-GoossensAG #memory management #policy: Conservative open-page policy for mixed time-criticality memory controllers (SG, BA, KG), pp. 525–530.
SAC-2013-HuangMGM #multi #realtime #scalability: Throughput-constrained voltage and frequency scaling for real-time heterogeneous multiprocessors (PH, OM, KG, AMM), pp. 1517–1524.
DAC-2012-0001AG #memory management #realtime #runtime: Run-time power-down strategies for real-time SDRAM memory controllers (KC, BA, KG), pp. 988–993.
DATE-2012-GomonyWAWG #mobile #realtime: DRAM selection and configuration for real-time mobile systems (MDG, CW, BA, NW, KG), pp. 51–56.
DATE-2012-GoossensKAG #realtime: Memory-map selection for firm real-time SDRAM controllers (SG, TK, BA, KG), pp. 828–831.
DATE-2012-StefanMAG #multi #performance: A TDM NoC supporting QoS, multicast, and fast connection set-up (RAS, AMM, JAA, KG), pp. 1283–1288.
DATE-2011-AkessonG #architecture #integration #memory management #modelling #predict: Architectures and modeling of predictable memory controllers for improved system integration (BA, KG), pp. 851–856.
DATE-2011-NejadMG #quality: An FPGA bridge preserving traffic quality of service for on-chip network-based systems (ABN, MEM, KG), pp. 425–430.
DATE-2011-SchenkelaarsVG #network #scheduling: Optimal scheduling of switched FlexRay networks (TS, BV, KG), pp. 926–931.
DAC-2010-GoossensH #evolution #network: The aethereal network on chip after ten years: goals, evolution, lessons, and future (KG, AH), pp. 306–311.
DATE-2009-GoossensVN #debugging: A high-level debug environment for communication-centric debug (KG, BV, ABN), pp. 202–207.
DATE-2009-HanssonSG #composition #named #network #predict: Aelite: A flit-synchronous Network on Chip with composable and predictable services (AH, MS, KG), pp. 250–255.
DATE-2007-BrandCGB #communication: Congestion-controlled best-effort communication for networks-on-chip (JWvdB, CC, KG, TB), pp. 948–953.
DATE-2007-HanssonCG #configuration management #multi #network: Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip (AH, MC, KG), pp. 954–959.
DATE-2006-MuraliCRGM #multi #network: A methodology for mapping multiple use-cases onto networks on chips (SM, MC, AR, KG, GDM), pp. 118–123.
DATE-DF-2006-SteenhofDNGL #architecture #network: Networks on chips for high-end consumer-electronics TV system architectures (FS, HD, BN, KG, RPL), pp. 148–153.
DATE-2005-GoossensDGPRR #design #network #performance #verification: A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification (KG, JD, OPG, SGP, AR, ER), pp. 1182–1187.