BibSLEIGH — Benny

Travelled to:

1 × Italy
2 × Germany
2 × USA
3 × France

Collaborated with:

K.Goossens M.D.Gomony K.Chandrasekar C.Weis N.Wehn S.Goossens H.I.Ali L.M.Pinho H.Shah A.Knoll V.Rodrigues S.M.d.Sousa M.Florido T.Kouters J.Garside N.C.Audsley K.G.W.Goossens M.Koedam

Talks about:

time (11) real (7) control (6) system (6) memori (6) dram (6) analysi (3) sdram (3) power (3) optim (3)

Person: Benny Akesson

DBLP: Akesson:Benny

Contributed to:

2015

2014

2013

2012

2011

Wrote 14 papers:

DATE-2015-GomonyGAAG #memory management #realtime #scalability: A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems (MDG, JG, BA, NCA, KGWG), pp. 193–198.
PDP-2015-AliAP #data flow #graph #parametricity #realtime: Generalized Extraction of Real-Time Parameters for Homogeneous Synchronous Dataflow Graphs (HIA, BA, LMP), pp. 701–710.
DATE-2014-0001GWKAWG #optimisation #performance #runtime: Exploiting expendable process-margins in DRAMs for run-time performance optimization (KC, SG, CW, MK, BA, NW, KG), pp. 1–6.
DATE-2014-GomonyAG #optimisation #performance #realtime: Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems (MDG, BA, KG), pp. 1–6.
DAC-2013-0001WAWG #approach #empirical #estimation #towards: Towards variation-aware system-level power estimation of DRAMs: an empirical approach (KC, CW, BA, NW, KG), p. 8.
DATE-2013-0001WAWG #3d #energy #modelling: System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs (KC, CW, BA, NW, KG), pp. 236–241.
DATE-2013-GomonyAG #architecture #memory management #multi #realtime: Architecture and optimal configuration of a real-time multi-channel memory controller (MDG, BA, KG), pp. 1307–1312.
DATE-2013-GoossensAG #memory management #policy: Conservative open-page policy for mixed time-criticality memory controllers (SG, BA, KG), pp. 525–530.
DATE-2013-ShahKA #analysis #bound: Bounding SDRAM interference: detailed analysis vs. latency-rate analysis (HS, AK, BA), pp. 308–313.
PADL-2013-RodriguesASF #abstraction #analysis #composition #declarative #multi #using: A Declarative Compositional Timing Analysis for Multicores Using the Latency-Rate Abstraction (VR, BA, SMdS, MF), pp. 43–59.
DAC-2012-0001AG #memory management #realtime #runtime: Run-time power-down strategies for real-time SDRAM memory controllers (KC, BA, KG), pp. 988–993.
DATE-2012-GomonyWAWG #mobile #realtime: DRAM selection and configuration for real-time mobile systems (MDG, CW, BA, NW, KG), pp. 51–56.
DATE-2012-GoossensKAG #realtime: Memory-map selection for firm real-time SDRAM controllers (SG, TK, BA, KG), pp. 828–831.
DATE-2011-AkessonG #architecture #integration #memory management #modelling #predict: Architectures and modeling of predictable memory controllers for improved system integration (BA, KG), pp. 851–856.