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Travelled to:
1 × Canada
1 × India
1 × Korea
1 × Poland
1 × Sweden
2 × USA
Collaborated with:
R.Driessel C.Habla L.Forstner C.Yugma A.Bilyk J.Zimmermann Jens Rocholl T.Ponsignon H.Ehm Necip Baris Kacar Reha Uzsoy U.Hönig W.Schiffmann Timm Ziarnetzky Denny Kopp Detlef Pabst M.Stehli
Talks about:
schedul (5) job (5) semiconductor (4) parallel (4) product (4) heurist (4) complex (4) plan (4) base (4) manufactur (3)

Person: Lars Mönch

DBLP DBLP: M=ouml=nch:Lars

Contributed to:

CASE 20152015
CASE 20122012
ICEIS v1 20122012
CASE 20102010
CASE 20092009
CASE 20082008
CASE 20072007
CASE 20172017
CASE 20182018

Wrote 14 papers:

CASE-2015-ForstnerM #optimisation #safety #using
Using simulation-based optimization to determine production strategies and safety stock levels in semiconductor supply chains (LF, LM), pp. 655–656.
CASE-2015-MonchY #constraints #parallel #scheduling
Scheduling jobs on parallel machines with qualification constraints (LM, CY), pp. 657–658.
CASE-2012-BilykM #heuristic #parallel #problem #search-based
Variable neighborhood search-based subproblem solution procedures for a parallel shifting bottleneck heuristic for complex job shops (AB, LM), pp. 419–424.
CASE-2012-DriesselM #case study #composition #heuristic #scheduling
An exploratory study of a decomposition heuristic for complex shop scheduling with transportation (RD, LM), pp. 413–418.
ICEIS-v1-2012-Monch #component #design #implementation #scheduling
Design and Implementation of a Service-based Scheduling Component for Complex Manufacturing Systems (LM), pp. 284–290.
CASE-2010-DriesselHMS #architecture #assessment #heuristic #parallel #performance #scheduling
A parallel shifting bottleneck heuristic for scheduling complex job shops: Architecture and performance assessment (RD, UH, LM, WS), pp. 81–86.
CASE-2009-MonchZ #case study #experience #prototype #state of the art #web #web service
Providing production planning and control functionality by web services: State of the art and experiences with prototypes (LM, JZ), pp. 495–500.
CASE-2008-Monch #heuristic #parallel
Heuristics to minimize total weighted tardiness of jobs on unrelated parallel machines (LM), pp. 572–577.
CASE-2007-HablaDMPE
A Short-Term Forecast Method for Demand Quantities in Semiconductor Manufacturing (CH, RD, LM, TP, HE), pp. 94–99.
CASE-2007-HablaMD #approach #capacity #finite
A Finite Capacity Production Planning Approach for Semiconductor Manufacturing (CH, LM, RD), pp. 82–87.
CASE-2017-RochollM #algorithm #multi #order #problem #scheduling #search-based
Genetic algorithms for a single-machine multiple orders per job scheduling problem with a common due date (JR, LM), pp. 1038–1039.
CASE-2017-ZiarnetzkyMPE #process
Rolling horizon planning with engineering activities in semiconductor supply chains (TZ, LM, TP, HE), pp. 1024–1025.
CASE-2018-KacarMU #problem #reduction #using
Problem Reduction Approaches for Production Planning Using Clearing Functions (NBK, LM, RU), pp. 931–938.
CASE-2018-KoppMPS #assessment #performance
Simulation-based Performance Assessment of Tool Requalification Strategies in Wafer Fabs (DK, LM, DP, MS), pp. 638–641.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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