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Travelled to:
1 × France
1 × Germany
1 × USA
1 × United Kingdom
Collaborated with:
E.Pastor J.Cortadella M.Solé A.B.Smirnov O.Roig A.L.Semenov A.Yakovlev
Talks about:
circuit (3) verif (3) asynchron (2) concurr (2) system (2) synthesi (1) synchron (1) independ (1) travers (1) transyt (1)

Person: Marco A. Peña

DBLP DBLP: Pe=ntilde=a:Marco_A=

Contributed to:

CAV 20052005
DATE 20032003
DATE 20022002
DAC 19971997

Wrote 5 papers:

CAV-2005-PastorPS #concurrent #named #verification
TRANSYT: A Tool for the Verification of Asynchronous Concurrent Systems (EP, MAP, MS), pp. 424–428.
DATE-2003-PastorP #concurrent #simulation #traversal #verification
Combining Simulation and Guided Traversal for the Verification of Concurrent Systems (EP, MAP), pp. 11158–11159.
DATE-2002-PenaCSP #case study #verification
A Case Study for the Verification of Complex Timed Circuits: IPCMOS (MAP, JC, ABS, EP), pp. 44–51.
DAC-1997-RoigCPP #automation #generative
Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits (OR, JC, MAP, EP), pp. 620–625.
DAC-1997-SemenovYPPC #independence #synthesis
Synthesis of Speed-Independent Circuits from STG-Unfolding Segment (ALS, AY, EP, MAP, JC), pp. 16–21.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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