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Travelled to:
1 × Germany
1 × Italy
6 × France
9 × USA
Collaborated with:
M.Kishinevsky L.Lavagno A.Kondratyev E.Pastor D.Bañeres A.Yakovlev M.G.Oms M.A.Peña J.Carmona R.Clarisó D.Bufistov E.Tuncer B.Grundmann A.B.Smirnov O.Roig J.Júlvez K.Lwin C.P.Sotiriou A.L.Semenov K.S.Stevens S.Rotem S.M.Burns R.Ginosar M.Roncken M.Massot S.Moral C.Passerone Y.Watanabe A.L.Sangiovanni-Vincentelli
Talks about:
asynchron (7) circuit (7) synthesi (5) elast (5) synchron (4) automat (4) system (3) encod (3) independ (2) generat (2)

Person: Jordi Cortadella

DBLP DBLP: Cortadella:Jordi

Contributed to:

DATE 20102010
DAC 20092009
DATE 20092009
DAC 20072007
DATE 20072007
DAC 20062006
DAC 20042004
DATE v2 20042004
SAS 20042004
DATE 20022002
DAC 20002000
DAC 19991999
DAC 19981998
DATE 19981998
DAC 19971997
ED&TC 19971997
DAC 19961996

Wrote 22 papers:

DATE-2010-OmsCBK #architecture #automation #pipes and filters
Automatic microarchitectural pipelining (MGO, JC, DB, MK), pp. 961–964.
DAC-2009-BufistovCOJK #evaluation
Retiming and recycling for elastic systems with early evaluation (DB, JC, MGO, JJ, MK), pp. 288–291.
Speculation in elastic systems (MGO, JC, MK), pp. 292–295.
DAC-2009-TuncerCL #adaptation
Enabling adaptability through elastic clocks (ET, JC, LL), pp. 8–10.
DATE-2009-BaneresCK #design
Variable-latency design by function speculation (DB, JC, MK), pp. 1704–1709.
DAC-2007-CortadellaK #evaluation
Synchronous Elastic Circuits with Early Evaluation and Token Counterflow (JC, MK), pp. 416–419.
Layout-aware gate duplication and buffer insertion (DB, JC, MK), pp. 1367–1372.
DAC-2006-CarmonaC #encoding #scalability
State encoding of large asynchronous controllers (JC, JC), pp. 939–944.
DAC-2006-CortadellaKG #architecture #synthesis
Synthesis of synchronous elastic architectures (JC, MK, BG), pp. 657–662.
DAC-2004-BaneresCK #paradigm #recursion
A recursive paradigm to solve Boolean relations (DB, JC, MK), pp. 416–421.
DATE-v2-2004-CortadellaKLLS #approach #automation
From Synchronous to Asynchronous: An Automatic Approach (JC, AK, LL, KL, CPS), pp. 1368–1369.
SAS-2004-ClarisoC #abstract domain
The Octahedron Abstract Domain (RC, JC), pp. 312–327.
DATE-2002-PenaCSP #case study #verification
A Case Study for the Verification of Complex Timed Circuits: IPCMOS (MAP, JC, ABS, EP), pp. 44–51.
DAC-2000-CortadellaKLMMPWS #embedded #generative #scheduling
Task generation and compile-time scheduling for mixed data-control embedded software (JC, AK, LL, MM, SM, CP, YW, ALSV), pp. 489–494.
DAC-1999-KondratyevCKLY #automation #optimisation #synthesis
Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems (AK, JC, MK, LL, AY), pp. 110–115.
DAC-1999-StevensRBCGKR #performance
CAD Directions for High Performance Asynchronous Circuits (KSS, SR, SMB, JC, RG, MK, MR), pp. 116–121.
DAC-1998-KishinevskyCK #analysis #interface #specification #synthesis
Asynchronous Interface Specification, Analysis and Synthesis (MK, JC, AK), pp. 2–7.
DATE-1998-PastorC #analysis #encoding #performance #petri net
Efficient Encoding Schemes for Symbolic Analysis of Petri Nets (EP, JC), pp. 790–795.
DAC-1997-RoigCPP #automation #generative
Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits (OR, JC, MAP, EP), pp. 620–625.
DAC-1997-SemenovYPPC #independence #synthesis
Synthesis of Speed-Independent Circuits from STG-Unfolding Segment (ALS, AY, EP, MAP, JC), pp. 16–21.
EDTC-1997-CortadellaKKLY #composition #independence
Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis (JC, MK, AK, LL, AY), pp. 98–105.
DAC-1996-CortadellaKKLY #encoding #synthesis #tool support
Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis (JC, MK, AK, LL, AY), pp. 63–66.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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