Travelled to:2 × USA
Collaborated with:Y.Chen W.Wen Y.Zhang H.Li J.Hu H.H.Li X.Liu B.Liu B.Li Y.Wang H.Jiang M.Barnell Q.Wu J.Yang
Talks about:high (3) memori (2) explor (2) design (2) gpgpu (2) architectur (1) reconfigur (1) neuromorph (1) racetrack (1) versatil (1)
Person: Mengjie Mao
DBLP: Mao:Mengjie
Contributed to:
20152014Wrote 4 papers:
- DAC-2015-LiuMLLCLWJBWY #configuration management #design #named
- RENO: a high-efficient reconfigurable neuromorphic computing accelerator design (XL, MM, BL, HL, YC, BL, YW, HJ, MB, QW, JY), p. 6.
- DAC-2015-MaoHCL #named
- VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications (MM, JH, YC, HL), p. 6.
- DAC-2014-MaoWZCL #architecture #memory management #using
- Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory (MM, WW, YZ, YC, HHL), p. 6.
- DAC-2014-WenZMC #design #memory management #strict
- State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System (WW, YZ, MM, YC), p. 6.