BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
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Travelled to:
1 × India
3 × Germany
5 × France
9 × USA
Collaborated with:
H.Li Y.Zhang W.Wen X.Wang B.Liu Y.Xie Y.Wang M.Mao X.Chen H.H.Li C.J.Xue R.E.Pino J.Hu B.Li J.Guo H.Yang G.Sun Q.Wu J.Yang Y.Zhang K.Roy W.Xu T.Zhang D.Niu X.Dong M.Hu X.Li T.Huang R.Luo B.Yan Z.Mao M.Dong J.(.Zhang Y.Chen C.Xu V.Balakrishnan C.Koh M.Barnell S.Gu E.H.Sha Q.Zhuge W.Wu J.Zheng M.Zhao X.Bi C.Zhang Y.Li A.K.Jones B.Zhao J.Li S.Bhunia T.N.Vijaykumar H.Jiang D.Wang E.Eken R.V.Joshi N.Xu S.Li J.Li L.Shi Q.Li Y.Xu W.Zhu X.Wu C.Wu Q.Qiu W.Wen C.Wu X.Hu T.Ho T.Tang L.Xia W.Zhang Y.Joo Y.Chen M.Sun L.E.Burke H.Chen Y.Bai Y.Li C.Li W.Jia C.Liu C.Yang L.Song Z.Li X.Liu J.Yang
Talks about:
design (9) ram (9) memori (8) memristor (7) system (7) stt (7) comput (6) applic (6) neuromorph (5) storag (5)

Person: Yiran Chen

DBLP DBLP: Chen:Yiran

Contributed to:

DAC 20152015
DATE 20152015
DAC 20142014
DATE 20142014
DAC 20132013
DATE 20132013
DAC 20122012
DATE 20122012
DATE 20112011
DAC 20102010
DATE 20102010
HPCA 20102010
DAC 20092009
DATE 20092009
HPCA 20092009
DAC 20082008
HPCA 20032003
DATE 20022002

Wrote 39 papers:

DAC-2015-ChenCX #classification #named #power management #video
DaTuM: dynamic tone mapping technique for OLED display power saving based on video classification (XC, YC, CJX), p. 6.
DAC-2015-GuSZCH #embedded #memory management #performance
Area and performance co-optimization for domain wall memory in application-specific embedded systems (SG, EHMS, QZ, YC, JH), p. 6.
DAC-2015-GuoWHWLC #design #latency #named #novel #reduction
FlexLevel: a novel NAND flash storage system design for LDPC latency reduction (JG, WW, JH, DW, HL, YC), p. 6.
DAC-2015-LiuLCLWH #named
Vortex: variation-aware training for memristor X-bar (BL, HL, YC, XL, QW, TH), p. 6.
DAC-2015-LiuMLLCLWJBWY #configuration management #design #named
RENO: a high-efficient reconfigurable neuromorphic computing accelerator design (XL, MM, BL, HL, YC, BL, YW, HJ, MB, QW, JY), p. 6.
DAC-2015-LiuWLCWBQ #challenge #design #security
Cloning your mind: security challenges in cognitive system designs and their solutions (BL, CW, HL, YC, QW, MB, QQ), p. 5.
DAC-2015-LiuYYSLLCLWJ #design
A spiking neuromorphic design with resistive crossbar (CL, BY, CY, LS, ZL, BL, YC, HL, QW, HJ), p. 6.
DAC-2015-MaoHCL #named
VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications (MM, JH, YC, HL), p. 6.
DAC-2015-WenWHLHLC #framework #hybrid #scalability
An EDA framework for large scale hybrid neuromorphic computing systems (WW, CRW, XH, BL, TYH, XL, YC), p. 6.
DATE-2015-TangXLLCWY #network #question
Spiking neural network with RRAM: can we use it for real-world application? (TT, LX, BL, RL, YC, YW, HY), pp. 860–865.
DATE-2015-ZhangYWLC #design #logic #power management
Giant spin hall effect (GSHE) logic design for low power application (YZ, BY, WW, HL, YC), pp. 1000–1005.
DAC-2014-ChenCDZ #energy #smarttech
Demystifying Energy Usage in Smartphones (XC, YC, MD, J(Z), p. 5.
DAC-2014-EkenZWJLC #self
A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability (EE, YZ, WW, RVJ, HL, YC), p. 6.
DAC-2014-MaoWZCL #architecture #memory management #using
Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory (MM, WW, YZ, YC, HHL), p. 6.
DAC-2014-SunBMCCBLLJ #health #monitoring #named #smarttech
eButton: A Wearable Computer for Health Monitoring and Personal Assistance (MS, LEB, ZHM, YC, HCC, YB, YL, CL, WJ), p. 6.
DAC-2014-WenZMC #design #memory management #strict
State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System (WW, YZ, MM, YC), p. 6.
DATE-2014-0002LLCXY #big data #data analysis #energy #network #performance
Energy efficient neural networks for big data analytics (YW, BL, RL, YC, NX, HY), pp. 1–2.
DATE-2014-LiWCLY #named
ICE: Inline calibration for memristor crossbar-based computing engine (BL, YW, YC, HHL, HY), pp. 1–4.
Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine (BL, MH, HL, ZHM, YC, TH, WZ), p. 6.
DATE-2013-GuoWLLLC #named
DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems (JG, WW, YZ, SL, HL, YC), pp. 380–385.
DATE-2013-GuoYZC #hybrid #low cost
Low cost power failure protection for MLC NAND flash storage systems with PRAM/DRAM hybrid buffer (JG, JY, YZ, YC), pp. 859–864.
DATE-2013-LiSLXCX #adaptation
Cache coherence enabled adaptive refresh for volatile STT-RAM (JL, LS, QL, CJX, YC, YX), pp. 1247–1250.
DAC-2012-ChenZCZX #mobile #scalability #streaming #video
Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices (XC, JZ, YC, MZ, CJX), pp. 1000–1005.
DAC-2012-PinoLCHL #case study #modelling #statistics
Statistical memristor modeling and case study in neuromorphic computing (REP, HHL, YC, MH, BL), pp. 585–590.
DAC-2012-WenZCWX #analysis #named #performance #reliability #scalability #statistics
PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method (WW, YZ, YC, YW, YX), pp. 1191–1196.
DATE-2012-BiZLCP #design
Spintronic memristor based temperature sensor design with CMOS current reference (XB, CZ, HL, YC, REP), pp. 1301–1306.
DATE-2012-ZhangWLJC #design #symmetry
Asymmetry of MTJ switching and its implication to STT-RAM designs (YZ, XW, YL, AKJ, YC), pp. 1313–1318.
DATE-2012-ZhaoYZCL #architecture #array #memory management
Architecting a common-source-line array for bipolar non-volatile memory devices (BZ, JY, YZ, YC, HL), pp. 1451–1454.
DATE-2011-ChenLCP #3d #design #memory management #named
3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers (YCC, HL, YC, REP), pp. 583–586.
DAC-2010-NiuCXX #process
Impact of process variations on emerging memristor (DN, YC, CX, YX), pp. 877–882.
DATE-2010-ChenLWZXZ #memory management #random #self
A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM) (YC, HL, XW, WZ, WX, TZ), pp. 148–153.
Spintronic memristor devices and application (XW, YC), pp. 667–672.
HPCA-2010-SunJCNXCL #architecture #energy #hybrid #performance
A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement (GS, YJ, YC, DN, YX, YC, HL), pp. 1–12.
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing (WX, YC, XW, TZ), pp. 87–90.
DATE-2009-LiC #architecture #bibliography #memory management #tool support
An overview of non-volatile memory technology and the implication for tools and architectures (HL, YC), pp. 731–736.
HPCA-2009-SunDXLC #3d #architecture #novel
A novel architecture of the 3D stacked MRAM L2 cache for CMPs (GS, XD, YX, JL, YC), pp. 239–249.
DAC-2008-DongWSXLC #3d #architecture #evaluation #memory management #ram
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement (XD, XW, GS, YX, HHL, YC), pp. 554–559.
HPCA-2003-LiBCVR #reduction
Deterministic Clock Gating for Microprocessor Power Reduction (HL, SB, YC, TNV, KR), pp. 113–122.
DATE-2002-ChenBKR #reduction #using
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods (YC, VB, CKK, KR), pp. 931–935.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.