BibSLEIGH — Hai

Travelled to:

1 × India
2 × Germany
4 × France
6 × USA

Collaborated with:

Y.Chen M.Hu Q.Wu B.Liu Y.Zhang X.Bi K.Roy W.Wen R.E.Pino J.Hu M.Mao J.Guo M.A.Weldon A.Agarwal T.Huang B.Yan G.S.Rose Y.Chen M.Barnell W.Wu C.Zhang B.Zhao J.Yang Y.Zhang S.Bhunia T.N.Vijaykumar H.Jiang D.Wang X.Li E.Eken R.V.Joshi S.Li X.Wang W.Zhu W.Xu T.Zhang C.Wu Q.Qiu Z.Mao W.Zhang G.Sun Y.Joo Y.Chen D.Niu Y.Xie C.Liu C.Yang L.Song Z.Li X.Liu B.Li Y.Wang J.Yang

Talks about:

design (8) memristor (5) system (4) memori (4) ram (4) neuromorph (3) crossbar (3) storag (3) comput (3) applic (3)

Person: Hai Li

DBLP: Li:Hai

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2003

2002

Wrote 21 papers:

DAC-2015-GuoWHWLC #design #latency #named #novel #reduction: FlexLevel: a novel NAND flash storage system design for LDPC latency reduction (JG, WW, JH, DW, HL, YC), p. 6.
DAC-2015-LiuLCLWH #named: Vortex: variation-aware training for memristor X-bar (BL, HL, YC, XL, QW, TH), p. 6.
DAC-2015-LiuMLLCLWJBWY #configuration management #design #named: RENO: a high-efficient reconfigurable neuromorphic computing accelerator design (XL, MM, BL, HL, YC, BL, YW, HJ, MB, QW, JY), p. 6.
DAC-2015-LiuWLCWBQ #challenge #design #security: Cloning your mind: security challenges in cognitive system designs and their solutions (BL, CW, HL, YC, QW, MB, QQ), p. 5.
DAC-2015-LiuYYSLLCLWJ #design: A spiking neuromorphic design with resistive crossbar (CL, BY, CY, LS, ZL, BL, YC, HL, QW, HJ), p. 6.
DAC-2015-MaoHCL #named: VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications (MM, JH, YC, HL), p. 6.
DATE-2015-ZhangYWLC #design #logic #power management: Giant spin hall effect (GSHE) logic design for low power application (YZ, BY, WW, HL, YC), pp. 1000–1005.
DAC-2014-EkenZWJLC #self: A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability (EE, YZ, WW, RVJ, HL, YC), p. 6.
DAC-2013-LiuHLMCHZ: Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine (BL, MH, HL, ZHM, YC, TH, WZ), p. 6.
DATE-2013-BiWL #design: STT-RAM designs supporting dual-port accesses (XB, MAW, HL), pp. 853–858.
DATE-2013-GuoWLLLC #named: DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems (JG, WW, YZ, SL, HL, YC), pp. 380–385.
DAC-2012-HuLWR #array #hardware #using: Hardware realization of BSB recall function using memristor crossbar arrays (MH, HL, QW, GSR), pp. 498–503.
DATE-2012-BiZLCP #design: Spintronic memristor based temperature sensor design with CMOS current reference (XB, CZ, HL, YC, REP), pp. 1301–1306.
DATE-2012-ZhaoYZCL #architecture #array #memory management: Architecting a common-source-line array for bipolar non-volatile memory devices (BZ, JY, YZ, YC, HL), pp. 1451–1454.
DATE-2011-ChenLCP #3d #design #memory management #named: 3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers (YCC, HL, YC, REP), pp. 583–586.
DATE-2010-ChenLWZXZ #memory management #random #self: A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM) (YC, HL, XW, WZ, WX, TZ), pp. 148–153.
DATE-2010-LiH: Compact model of memristors and its application in computing systems (HL, MH), pp. 673–678.
HPCA-2010-SunJCNXCL #architecture #energy #hybrid #performance: A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement (GS, YJ, YC, DN, YX, YC, HL), pp. 1–12.
DATE-2009-LiC #architecture #bibliography #memory management #tool support: An overview of non-volatile memory technology and the implication for tools and architectures (HL, YC), pp. 731–736.
HPCA-2003-LiBCVR #reduction: Deterministic Clock Gating for Microprocessor Power Reduction (HL, SB, YC, TNV, KR), pp. 113–122.
DAC-2002-AgarwalLR #named #power management: DRG-cache: a data retention gated-ground cache for low power (AA, HL, KR), pp. 473–478.