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Travelled to:
1 × Germany
1 × USA
4 × France
Collaborated with:
A.Baghdadi P.Murugappa H.Moussa O.Muller R.Al-Khayat P.Reddy F.Clermidy A.R.Jafri D.Karakolah M.Rizk Y.Mohana Y.Atat
Talks about:
turbo (6) decod (6) multiprocessor (3) flexibl (3) equal (3) base (3) asip (3) network (2) design (2) binari (2)

Person: Michel Jézéquel

DBLP DBLP: J=eacute=z=eacute=quel:Michel

Contributed to:

DATE 20132013
DATE 20112011
DATE 20092009
DAC 20082008
DATE 20072007
DATE 20062006

Wrote 8 papers:

DATE-2013-MurugappaBJ #multi #standard
Parameterized area-efficient multi-standard turbo decoder (PM, AB, MJ), pp. 109–114.
DATE-2013-RizkBJMA #case study #design
Statically-scheduled application-specific processor design: a case-study on MMSE MIMO equalization (MR, AB, MJ, YM, YA), pp. 677–680.
DATE-2011-MurugappaABJ #architecture #flexibility #multi #throughput
A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding (PM, RAK, AB, MJ), pp. 228–233.
DATE-2011-ReddyCBJ #complexity #power management
A low complexity stopping criterion for reducing power consumption in turbo decoders (PR, FC, AB, MJ), pp. 649–654.
DATE-2009-JafriKBJ #flexibility #linear
ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications (ARJ, DK, AB, MJ), pp. 1620–1625.
DAC-2008-MoussaBJ #flexibility #multi #network
Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder (HM, AB, MJ), pp. 429–434.
DATE-2007-MoussaMBJ #communication #multi #network
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding (HM, OM, AB, MJ), pp. 654–659.
DATE-2006-MullerBJ #design #multi
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding (OM, AB, MJ), pp. 1330–1335.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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