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Travelled to:
1 × Germany
9 × USA
Collaborated with:
S.Subramaniam K.Puttaswamy M.Prvulovic P.G.Sassone D.S.Wills B.Pham A.Bhattacharjee Y.Eckert A.Bracy H.Wang M.R.Meswani S.Blagodurov D.Roberts J.Slice M.Ignatowski S.Ozdemir Y.Pan A.Das G.Memik A.N.Choudhary M.B.Healy M.Vittes M.Ekpanyapong C.S.Ballapuram S.K.Lim H.S.Lee
Talks about:
memori (4) microarchitectur (3) perform (3) depend (3) processor (2) thermal (2) scalabl (2) predict (2) increas (2) exploit (2)

Person: Gabriel H. Loh

DBLP DBLP: Loh:Gabriel_H=

Contributed to:

HPCA 20152015
HPCA 20142014
DAC 20102010
HPCA 20092009
HPCA 20082008
DAC 20072007
HPCA 20072007
DATE 20062006
HPCA 20062006
LCTES 20052005

Wrote 10 papers:

HPCA-2015-MeswaniBRSIL #approach #architecture #memory management
Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories (MRM, SB, DR, JS, MI, GHL), pp. 126–136.
HPCA-2014-PhamBEL #clustering
Increasing TLB reach by exploiting clustering in page translations (BP, AB, YE, GHL), pp. 558–567.
DAC-2010-OzdemirPDMLC #3d #architecture #parametricity
Quantifying and coping with parametric variations in 3D-stacked microarchitectures (SO, YP, AD, GM, GHL, ANC), pp. 144–149.
HPCA-2009-SubramaniamBWL #optimisation #performance
Criticality-based optimizations for efficient load processing (SS, AB, HW, GHL), pp. 419–430.
HPCA-2008-SubramaniamPL #dependence #memory management #named #predict #smt
PEEP: Exploiting predictability of memory dependences in SMT processors (SS, MP, GHL), pp. 137–148.
DAC-2007-PuttaswamyL #3d #scalability
Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors (KP, GHL), pp. 622–625.
HPCA-2007-PuttaswamyL #3d #architecture
Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors (KP, GHL), pp. 193–204.
DATE-2006-HealyVEBLLL #architecture #performance #trade-off
Microarchitectural floorplanning under performance and thermal tradeoff (MBH, MV, ME, CSB, SKL, HHSL, GHL), pp. 1288–1293.
HPCA-2006-SubramaniamL #dependence #memory management #predict #scalability #scheduling
Store vectors for scalable memory dependence prediction and scheduling (SS, GHL), pp. 65–76.
LCTES-2005-SassoneWL #dependence #embedded #performance
Static strands: safely collapsing dependence chains for increasing embedded power efficiency (PGS, DSW, GHL), pp. 127–136.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.