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Travelled to:
4 × USA
Collaborated with:
A.K.Bose V.D.Agrawal H.N.Nham E.Pacas-Skewes A.Gupta A.E.Dunlop D.N.Deutsch M.F.Jukl M.Wiesel C.Lo K.W.Wu
Talks about:
simul (3) circuit (1) bipolar (1) weight (1) layout (1) design (1) critic (1) optim (1) fault (1) array (1)

Person: Patrick Kozak

DBLP DBLP: Kozak:Patrick

Contributed to:

DAC 19841984
DAC 19831983
DAC 19821982
DAC 19801980

Wrote 4 papers:

DAC-1984-DunlopADJKW #layout #optimisation #using
Chip layout optimization using critical path weighting (AED, VDA, DND, MFJ, PK, MW), pp. 133–136.
DAC-1983-KozakBG #array #design #simulation
Design aids for the simulation of bipolar gate arrays (PK, AKB, AG), pp. 286–292.
DAC-1982-BoseKLNPW #fault
A fault simulator for MOS LSI circuits (AKB, PK, CYL, HNN, EPS, KWW), pp. 400–409.
A mixed-mode simulator (VDA, AKB, PK, HNN, EPS), pp. 618–625.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.