Travelled to:1 × France
2 × USA
Collaborated with:E.Beyne G.V.d.Plas A.Vignon S.Cosemans W.Dehaene M.Facchini S.Bansal J.C.Rey A.Yang M.Jang L.C.Lu P.Magarshack R.Radojcic
Talks about:interconnect (1) architectur (1) technolog (1) heterogen (1) develop (1) context (1) system (1) leakag (1) integr (1) driver (1)
Person: Pol Marchal
DBLP: Marchal:Pol
Contributed to:
20112010
2009Wrote 3 papers:
- DAC-2011-BeyneMP #3d #development #integration
- 3D heterogeneous system integration: application driver for 3D technology development (EB, PM, GVdP), p. 213.
- DAC-2010-BansalRYJLMMR #3d #question
- 3-D stacked die: now or future? (SB, JCR, AY, MSJ, LCL, PM, PM, RR), pp. 298–299.
- DATE-2009-VignonCDMF #3d #architecture #novel
- A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context (AV, SC, WD, PM, MF), pp. 929–933.