BibSLEIGH — Wim

Travelled to:

2 × USA
3 × France
5 × Germany

Collaborated with:

Y.Vanderperren F.Catthoor C.Walravens M.Facchini V.Rozic B.Yang I.Verbauwhede P.Marchal S.Cosemans G.G.E.Gielen K.Maex A.Vignon N.Mentens J.V.Rethy H.Danneels V.D.Smedt P.Marchal B.Bougard D.C.Daly A.Chandrakasan H.Wang M.Miranda A.Sayinta G.Canverdi M.Pauwels A.Alshawa V.Sharma M.Ashouei J.Huisken P.Christie D.Draxelmayr E.Janssens T.Vucurevich T.Carlson M.Palkovic L.Benini I.Karageorgos M.Stucchi P.Raghavan J.Ryckaert Z.Tokei D.Verkest R.Baert S.Sakhare

Talks about:

sram (5) low (5) system (4) variabl (3) energi (3) effici (3) design (3) power (3) interconnect (2) architectur (2)

Person: Wim Dehaene

DBLP: Dehaene:Wim

Contributed to:

2015

2013

2012

2010

2009

2006

2005

2003

Wrote 16 papers:

DAC-2015-RozicYDV #generative #performance #random: Highly efficient entropy extraction for true random number generators on FPGAs (VR, BY, WD, IV), p. 6.
DATE-2015-KarageorgosSRRT #multi #variability: Impact of interconnect multiple-patterning variability on SRAMs (IK, MS, PR, JR, ZT, DV, RB, SS, WD), pp. 609–612.
DATE-2015-YangRMDV #embedded #framework #generative #on the fly #platform #random #testing: Embedded HW/SW platform for on-the-fly testing of true random number generators (BY, VR, NM, WD, IV), pp. 345–350.
DATE-2013-RethyDSDG #interface #network #power management: A low-power and low-voltage BBPLL-based sensor interface in 130nm CMOS for wireless sensor networks (JVR, HD, VDS, WD, GGEG), pp. 1431–1435.
DATE-2012-SharmaCAHCD #power management #variability: Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM (VS, SC, MA, JH, FC, WD), pp. 1042–1047.
DATE-2012-WalravensD #architecture #design #energy: Design of a low-energy data processing architecture for WSN nodes (CW, WD), pp. 570–573.
DATE-2010-FacchiniMCD #3d #configuration management #memory management: An RDL-configurable 3D memory tier to replace on-chip SRAM (MF, PM, FC, WD), pp. 291–294.
DAC-2009-WalravensVD #analysis #modelling #named #performance: ActivaSC: a highly efficient and non-intrusive extension for activity-based analysis of SystemC models (CW, YV, WD), pp. 172–177.
DATE-2009-FacchiniCVPCDBM #3d #evaluation #mobile #performance: System-level power/performance evaluation of 3D stacked DRAMs for mobile applications (MF, TC, AV, MP, FC, WD, LB, PM), pp. 923–928.
DATE-2009-VignonCDMF #3d #architecture #novel: A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context (AV, SC, WD, PM, MF), pp. 929–933.
DATE-2006-VanderperrenD #matlab #uml: From UML/SysML to Matlab/Simulink: current state and future perspectives (YV, WD), p. 93.
DATE-2005-BougardCDCD #energy #modelling #network #performance #standard: Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives (BB, FC, DCD, AC, WD), pp. 196–201.
DATE-2005-GielenDCDJMV #design #question: Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? (GGEG, WD, PC, DD, EJ, KM, TV), pp. 36–42.
DATE-2005-VanderperrenD #approach #complexity #design #uml: UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design (YV, WD), pp. 716–717.
DATE-2005-WangMDCM #analysis #embedded #energy #process #variability: Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules (HW, MM, WD, FC, KM), pp. 914–919.
DATE-2003-SayintaCPAD #abstraction #case study #using #verification: A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification (AS, GC, MP, AA, WD), pp. 20095–20100.