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Travelled to:
1 × Turkey
11 × USA
Collaborated with:
S.Devadas D.Lo A.Ferraiuolo D.Y.Deng Y.Wang M.Ismail R.C.Huang D.Zhang A.C.Myers A.H.Chan P.Jain L.Rudolph T.Chen E.Halberg J.W.Lee D.Zhang B.Gassend D.E.Clarke M.v.Dijk Rui Xu
Talks about:
time (6) memori (4) monitor (3) hardwar (3) inform (3) secur (3) flow (3) cach (3) run (3) overhead (2)

Person: G. Edward Suh

DBLP DBLP: Suh:G=_Edward

Contributed to:

ASPLOS 20152015
DAC 20152015
HPCA 20152015
HPCA 20142014
DAC 20122012
ASPLOS 20102010
DAC 20092009
DAC 20072007
ASPLOS 20042004
DAC 20032003
HPCA 20032003
HPCA 20022002
ASPLOS 20172017

Wrote 14 papers:

ASPLOS-2015-ZhangWSM #data flow #design #hardware #information management #security
A Hardware Design Language for Timing-Sensitive Information-Flow Security (DZ, YW, GES, ACM), pp. 503–516.
DAC-2015-IsmailLS #performance #worst-case
Improving worst-case cache performance through selective bypassing and register-indexed cache (MI, DL, GES), p. 6.
HPCA-2015-LoCIS #monitoring #runtime #using
Run-time monitoring with adjustable overhead using dataflow-guided filtering (DL, TC, MI, GES), pp. 662–674.
HPCA-2014-HuangHFS #concurrent #data transformation #detection #metadata #runtime
Low-overhead and high coverage run-time race detection through selective meta-data management (RCH, EH, AF, GES), pp. 96–107.
HPCA-2014-WangFS #memory management
Timing channel protection for a shared memory controller (YW, AF, GES), pp. 225–236.
DAC-2012-LoS #analysis #execution #monitoring #parallel #runtime #worst-case
Worst-case execution time analysis for parallel run-time monitoring (DL, GES), pp. 421–429.
ASPLOS-2010-HuangDS #multi #named #performance
Orthrus: efficient software integrity protection on multi-cores (RCH, DYD, GES), pp. 371–384.
DAC-2009-DengCS #authentication #hardware #performance #simulation
Hardware authentication leveraging performance limits in detailed simulations and emulations (DYD, AHC, GES), pp. 682–687.
DAC-2007-SuhD #authentication #generative #physics
Physical Unclonable Functions for Device Authentication and Secret Key Generation (GES, SD), pp. 9–14.
ASPLOS-2004-SuhLZD #data flow #execution #information management
Secure program execution via dynamic information flow tracking (GES, JWL, DZ, SD), pp. 85–96.
DAC-2003-JainSD #embedded
Embedded intelligent SRAM (PJ, GES, SD), pp. 869–874.
HPCA-2003-GassendSCDD #memory management #performance #verification
Caches and Hash Trees for Efficient Memory Integrity Verification (BG, GES, DEC, MvD, SD), pp. 295–306.
HPCA-2002-SuhDR #clustering #memory management #monitoring #scheduling
A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning (GES, SD, LR), pp. 117–128.
ASPLOS-2017-FerraiuoloXZMS #analysis #architecture #data flow #hardware #security #verification
Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis (AF, RX, DZ, ACM, GES), pp. 555–568.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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