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Travelled to:
1 × Italy
1 × Spain
10 × France
4 × USA
8 × Germany
Collaborated with:
F.Corno M.Rebaudengo G.Squillero M.Violante P.Bernardi P.Prinetto S.Gai L.Sterpone D.Sabena E.Sánchez G.Cumani M.Schillaci G.Cabodi P.Camurati A.Riefert M.Sauer B.Becker L.Carro O.Goloubeva P.L.Montessoro C.Meinhardt R.Reis G.Masera F.Quaglio F.L.Kastensmidt M.Torchiano S.Chiusano M.Gilli R.Cantoro R.Aitken G.Fey Z.T.Kalbarczyk F.Reichenbach M.Bonazza O.Ballan A.Manzone A.Pincetti M.Lajolo L.Lavagno A.Benso R.Ubar L.M.Ciganda P.Cheynet B.Nicolescu R.Velazco E.M.Rudnick R.Vietti A.Ellis A.Touati A.Bosio L.Dilillo P.Girard A.Virazel L.Berrojo I.González L.Entrena C.López L.A.Bautista-Gomez F.Cappello N.DeBardeleben B.Fang S.Gurumurthi K.Pattabiraman P.Rech M.Bellato D.Bortolato A.Candelori M.Ceschia A.Paccagnella P.Zambolin
Talks about:
test (19) generat (10) processor (8) circuit (8) automat (8) algorithm (7) techniqu (7) effect (7) new (7) sequenti (6)

Person: Matteo Sonza Reorda

DBLP DBLP: Reorda:Matteo_Sonza

Contributed to:

DATE 20152015
DATE 20142014
DATE 20132013
DATE 20122012
PDP 20122012
DATE 20092009
DATE 20082008
DATE 20072007
DATE 20062006
DATE 20052004
DATE 20052005
DATE v1 20042004
DATE 20032003
SAC 20032003
DATE 20022002
SAC 20022002
DATE 20012001
SAC 20012001
SCAM 20012001
DATE 20002000
DATE 19991999
DATE 19981998
SAC 19981998
ED&TC 19971997
SAC 19971997
PDP 19951995
EDAC-ETC-EUROASIC 19941994
PDP 19941994
PDP 19931993
DAC 19921992
CAV 19901990

Wrote 42 papers:

DATE-2015-RiefertCSRB #automation #generative #on the #source code
On the automatic generation of SBST test programs for in-field test (AR, RC, MS, MSR, BB), pp. 1186–1191.
DATE-2015-TouatiBDGVBR #functional #power management #source code #testing
Exploring the impact of functional test programs re-used for power-aware testing (AT, AB, LD, PG, AV, PB, MSR), pp. 1277–1280.
DATE-2014-Bautista-GomezCCDFGPRR #how #named #reliability
GPGPUs: How to combine high computational power with high reliability (LABG, FC, LC, ND, BF, SG, KP, PR, MSR), pp. 1–9.
DATE-2014-RiefertCSBRB #approach #automation #effectiveness #fault #functional #generative #testing
An effective approach to automatic functional processor test generation for small-delay faults (AR, LMC, MS, PB, MSR, BB), pp. 1–6.
DATE-2013-AitkenFKRR #analysis #how #question #reliability
Reliability analysis reloaded: how will we survive? (RA, GF, ZTK, FR, MSR), pp. 358–367.
DATE-2013-BernardiBSRB #embedded #fault #identification #online
On-line functionally untestable fault identification in embedded processor cores (PB, MB, ES, MSR, OB), pp. 1462–1467.
DATE-2012-SabenaRS #algorithm #testing
A new SBST algorithm for testing the register file of VLIW processors (DS, MSR, LS), pp. 412–417.
PDP-2012-SterponeSR #approach #fault #injection #testing
A New Fault Injection Approach for Testing Network-on-Chips (LS, DS, MSR), pp. 530–535.
DATE-2009-ReordaVMR #embedded #low cost
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips (MSR, MV, CM, RR), pp. 352–357.
DATE-2008-BernardiR #novel #testing
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers (PB, MSR), pp. 194–199.
DATE-2007-SanchezSSR #automation #effectiveness #generative #interactive #source code
Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor (ES, MS, GS, MSR), pp. 1158–1163.
DATE-2006-BernardiSSSR #cost analysis #effectiveness
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs (PB, ES, MS, GS, MSR), pp. 412–417.
DATE-2005-BernardiMQR04 #approach #logic #testing #using
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study (PB, GM, FQ, MSR), pp. 228–233.
DATE-2005-KastensmidtSCR #composition #design #logic #on the
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs (FLK, LS, LC, MSR), pp. 1290–1295.
DATE-v1-2004-BellatoBBCCPRRVZ #memory management
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA (MB, PB, DB, AC, MC, AP, MR, MSR, MV, PZ), pp. 584–589.
DATE-v1-2004-GoloubevaRV #automation #generative #validation
Automatic Generation of Validation Stimuli for Application-Specific Processors (OG, MSR, MV), pp. 188–193.
DATE-2003-BernardiRRV #approach #embedded #programmable
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories (PB, MR, MSR, MV), pp. 10720–10725.
DATE-2003-CornoCRS #automation #generative
Fully Automatic Test Program Generation for Microprocessor Cores (FC, GC, MSR, GS), pp. 11006–11011.
DATE-2003-RebaudengoRV #analysis #fault #pipes and filters
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor (MR, MSR, MV), pp. 10602–10607.
SAC-2003-CornoCRS #automation #generative #pipes and filters
Automatic Test Program Generation for Pipeline Processors (FC, GC, MSR, GS), pp. 736–740.
DATE-2002-BerrojoGCRSEL #injection
New Techniques for Speeding-Up Fault-Injection Campaigns (LB, IG, FC, MSR, GS, LE, CL), pp. 847–852.
SAC-2002-CornoRS #algorithm
An evolutionary algorithm for reducing integrated-circuit test application time (FC, MSR, GS), pp. 608–612.
DATE-2001-CheynetNVRRV #automation #evaluation #program transformation #safety
System safety through automatic high-level code transformations: an experimental evaluation (PC, BN, RV, MR, MSR, MV), pp. 297–301.
DATE-2001-CornoRSV #on the
On the test of microprocessor IP cores (FC, MSR, GS, MV), pp. 209–213.
SAC-2001-CornoRS #architecture #effectiveness #evolution
Evolving effective CA/CSTP: BIST architectures for sequential circuits (FC, MSR, GS), pp. 345–350.
SCAM-2001-RebaudengoRVT #compilation #generative #text-to-text
A Source-to-Source Compiler for Generating Dependable Software (MR, MSR, MV, MT), pp. 35–44.
DATE-2000-CornoRSMP #automation #experience #generative #industrial #validation
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience (FC, MSR, GS, AM, AP), pp. 385–389.
DATE-2000-LajoloRRVL #co-evolution #dependence #design #framework
Evaluating System Dependability in a Co-Design Framework (ML, MR, MSR, MV, LL), pp. 586–590.
DATE-1999-CornoRS #algorithm #approximate #equivalence #search-based #verification
Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms (FC, MSR, GS), pp. 754–755.
DATE-1998-CornoPRV
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection (FC, PP, MSR, MV), pp. 670–677.
DATE-1998-RudnickVECPR #generative #performance #testing #using
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques (EMR, RV, AE, FC, PP, MSR), pp. 570–576.
SAC-1998-CornoRS #algorithm #optimisation
The selfish gene algorithm: a new evolutionary optimization strategy (FC, MSR, GS), pp. 349–355.
EDTC-1997-BensoPRRU #approach #fault #graph #low level
A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs (AB, PP, MR, MSR, RU), pp. 560–565.
EDTC-1997-ChiusanoCPR #graph #hybrid #problem
Hybrid symbolic-explicit techniques for the graph coloring problem (SC, FC, PP, MSR), pp. 422–426.
EDTC-1997-CornoPRR #sequence #testing
New static compaction techniques of test sequences for sequential circuits (FC, PP, MR, MSR), pp. 37–43.
SAC-1997-CornoPRR #algorithm #generative #named
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits (FC, PP, MR, MSR), pp. 228–232.
PDP-1995-GaiRR #algorithm #parallel #using
An improved data parallel algorithm for Boolean function manipulation using BDDs (SG, MR, MSR), pp. 33–41.
EDAC-1994-GaiMR #fault #named #performance
TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits (SG, PLM, MSR), pp. 46–50.
PDP-1994-CabodiGRR #architecture #parallel
A BDD Package For A Massively Parallel SIMD Architecture (GC, SG, MR, MSR), pp. 212–219.
PDP-1993-RebaudengoR #algorithm #analysis #migration #parallel #search-based
An experimental analysis of the effects of migration in parallel genetic algorithms (MR, MSR), pp. 232–238.
DAC-1992-CabodiCCGPR #traversal
A New Model for Improving symbolic Product Machine Traversal (GC, PC, FC, SG, PP, MSR), pp. 614–619.
CAV-1990-CamuratiGPR #model checking #using
The Use of Model Checking in ATPG for Sequential Circuits (PC, MG, PP, MSR), pp. 86–95.

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