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Travelled to:
1 × France
1 × Germany
1 × USA
Collaborated with:
A.L.Sangiovanni-Vincentelli F.Balarin J.A.Rowson D.Densmore A.Simalatsar A.Davare F.Gregoretti F.Intini L.Lavagno L.M.Reyneri
Talks about:
design (3) interfac (2) transactor (1) methodolog (1) processor (1) implement (1) framework (1) synthesi (1) structur (1) protocol (1)

Person: Roberto Passerone

DBLP DBLP: Passerone:Roberto

Contributed to:

DATE 20092009
DATE 20062006
DAC 19981998
PDP 19961996

Wrote 4 papers:

DATE-2009-DensmoreSDPS #design #evaluation #framework #using
UMTS MPSoC design evaluation using a system level design framework (DD, AS, AD, RP, ALSV), pp. 478–483.
DATE-2006-BalarinP #functional #generative #interface #specification #verification
Functional verification methodology based on formal interface specification and transactor generation (FB, RP), pp. 1013–1018.
DAC-1998-PasseroneRS #automation #interface #protocol #synthesis
Automatic Synthesis of Interfaces Between Incompatible Protocols (RP, JAR, ALSV), pp. 8–13.
PDP-1996-GregorettiILPR #design #implementation
Design and Implementation of the Control Structure of the PAPRICA-3 Processor (FG, FI, LL, RP, LMR), pp. 290–296.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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