BibSLEIGH — Felice

Travelled to:

1 × Belgium
1 × Greece
1 × Israel
2 × France
3 × Canada
3 × Germany
6 × USA

Collaborated with:

A.L.Sangiovanni-Vincentelli H.Hsieh ∅ X.Chen A.Aziz V.Singhal R.Passerone Y.Watanabe R.K.Brayton L.Lavagno M.D.Natale G.Yang Y.Luo L.N.Bhuyan A.Jurecska M.D.DiBenedetto A.Saldanha J.Yu W.Wu J.Yang S.Cheng R.Hojati T.Kam S.C.Krishnan R.K.Ranjan T.R.Shiple S.Tasiran H.Wang

Talks about:

system (9) verif (5) network (4) automat (4) formal (4) embed (4) base (4) constraint (3) design (3) time (3)

Person: Felice Balarin

DBLP: Balarin:Felice

Contributed to:

2006

2005

2004

2003

2000

1998

1997

1996

1995

1994

1993

1992

Wrote 20 papers:

DATE-2006-BalarinP #functional #generative #interface #specification #verification: Functional verification methodology based on formal interface specification and transactor generation (FB, RP), pp. 1013–1018.
DATE-2006-YangCBHS #communication #framework #integration: Communication and co-simulation infrastructure for heterogeneous system integration (GY, XC, FB, HH, ALSV), pp. 462–467.
DATE-2005-YuWCHYB #architecture #design #network: Assertion-Based Design Exploration of DVS in Network Processor Architectures (JY, WW, XC, HH, JY, FB), pp. 92–97.
DATE-DF-2004-ChenLHBB #design #network: Utilizing Formal Assertions for System Design of Network Processors (XC, YL, HH, LNB, FB), pp. 126–133.
DAC-2003-ChenHBW #analysis #automation #constraints #logic: Automatic trace analysis for logic of constraints (XC, HH, FB, YW), pp. 460–465.
DATE-2003-ChenHBW #automation #constraints #generative #monitoring #simulation: Automatic Generation of Simulation Monitors from Quantitative Constraint Formula (XC, HH, FB, YW), pp. 11174–11175.
DAC-2000-HsiehBLS #design #embedded #performance: Efficient methods for embedded system design space exploration (HH, FB, LL, ALSV), pp. 607–612.
DAC-2000-NataleSB #constraints #scheduling: Task scheduling with RT constraints (MDN, ALSV, FB), pp. 483–488.
DATE-2000-Balarin #abstraction #analysis #automation #worst-case: Automatic Abstraction for Worst-Case Analysis of Discrete Systems (FB), pp. 494–501.
CAV-1998-Balarin #approach #concurrent #correctness #modelling #verification: Correctness of the Concurrent Approach to Symbolic Verification of Interleaved Models (FB), pp. 391–402.
LCTES-1998-Balarin #embedded #realtime: Priority Assignment for Embedded Reactive Real-Time Systems (FB), pp. 146–155.
DAC-1997-BalarinS #embedded #realtime #validation: Schedule Validation for Embedded Reactive Real-Time Systems (FB, ALSV), pp. 52–57.
DAC-1996-BalarinHJLS #embedded #network #verification: Formal Verification of Embedded Systems based on CFSM Networks (FB, HH, AJ, LL, ALSV), pp. 568–571.
CAV-1995-AzizBBDS #finite #state machine: Supervisory Control of Finite State Machines (AA, FB, RKB, MDD, AS), pp. 279–292.
CAV-1995-AzizSB #logic #probability: It Usually Works: The Temporal Logic of Stochastic Systems (AA, VS, FB), pp. 155–165.
CAV-1994-BalarinS #automation #invariant #network #on the: On the Automatic Computation of Network Invariants (FB, ALSV), pp. 234–246.
DAC-1994-AzizBCHKKRSSTWBS #named #verification: HSIS: A BDD-Based Environment for Formal Verification (AA, FB, STC, RH, TK, SCK, RKR, TRS, VS, ST, HYW, RKB, ALSV), pp. 454–459.
ICALP-1994-AzizSBBS: Equivalences for Fair Kripke Structures (AA, VS, FB, RKB, ALSV), pp. 364–375.
CAV-1993-BalarinS #approach: An Iterative Approach to Language Containment (FB, ALSV), pp. 29–40.
CAV-1992-BalarinS #verification: A Verification Strategy for Timing-Constrained Systems (FB, ALSV), pp. 151–163.