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Travelled to:
1 × USA
2 × Germany
4 × France
Collaborated with:
C.Lu S.Hsu H.Tung E.Shragowitz H.Tsai L.Lai S.Chen K.Lin T.Lin T.Lin A.Lu H.Lu E.Jang Y.Lin C.Hung C.Chuang
Talks about:
standard (3) design (3) cell (3) placement (2) structur (2) slack (2) gate (2) asic (2) transistor (1) simultan (1)

Person: Rung-Bin Lin

DBLP DBLP: Lin:Rung=Bin

Contributed to:

DATE 20152015
DATE 20132013
DATE 20122012
DATE 20112011
DATE 20102010
DATE 20072007
DAC 19921992

Wrote 7 papers:

DATE-2015-LuLJLHCL #standard
Simultaneous transistor pairing and placement for CMOS standard cells (AL, HJL, EJJ, YPL, CHH, CCC, RBL), pp. 1647–1652.
DATE-2013-LuL #multi
Slack budgeting and slack to length converting for multi-bit flip-flop merging (CCL, RBL), pp. 1837–1842.
DATE-2012-TsaiLL #analysis #configuration management #design
Design and analysis of via-configurable routing fabrics for structured ASICs (HPT, RBL, LCL), pp. 1479–1482.
DATE-2011-HsuL #optimisation
Clock gating optimization with delay-matching (SJH, RBL), pp. 643–648.
DATE-2010-ChenLTL #design #power management #standard
Power gating design for standard-cell-like structured ASICs (SYC, RBL, HHT, KWL), pp. 514–519.
DATE-2007-LinLTL #design #library #standard
Double-via-driven standard cell library design (TYL, THL, HHT, RBL), pp. 1212–1217.
DAC-1992-LinS #approach #fuzzy #logic #problem
Fuzzy Logic Approach to Placement Problem (RBL, ES), pp. 153–158.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.