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Travelled to:
1 × Austria
1 × Belgium
1 × Canada
1 × Cyprus
1 × Germany
1 × Poland
1 × Sweden
1 × The Netherlands
1 × United Kingdom
2 × France
6 × USA
Collaborated with:
C.R.Ramakrishnan T.Bultan M.Ouederni G.R.Santhanam R.Sinha P.S.Roop Z.Salcic F.Vasile Z.J.Oster V.Honavar Y.Hanna H.Rajan H.Sun R.R.Lutz P.Yang C.W.Keller D.Saha S.A.Smolka K.N.Kumar L.R.Pokorny R.He P.Jennings A.P.Ghosh H.Wu R.Sekar V.N.Venkatakrishnan S.Bhatkar D.C.DuVarney M.Mukund I.V.Ramakrishnan R.M.Verma
Talks about:
system (5) verif (5) model (4) check (4) parameter (3) composit (3) program (3) analysi (3) asynchron (2) approach (2)

♂ Person: Samik Basu

DBLP DBLP: Basu:Samik

Facilitated 2 volumes:

ASE 2013ExpertReviewPa
ASE 2013PrBoard

Contributed to:

ASE 20142014
DATE 20122012
POPL 20122012
VMCAI 20122012
ASE 20112011
ASE 20102010
KR 20102010
DATE 20092009
ESEC/FSE 20092009
SPLC 20092009
SEKE 20072007
TACAS 20062006
TACAS 20052005
SOSP 20032003
TACAS 20032003
TACAS 20022002
ICLP 20012001

Wrote 17 papers:

ASE-2014-BasuB #automation #bound #interactive #verification
Automatic verification of interactions in asynchronous systems with unbounded buffers (SB, TB), pp. 743–754.
DATE-2012-SinhaRSB #component #design #multi
Correct-by-construction multi-component SoC design (RS, PSR, ZS, SB), pp. 647–652.
POPL-2012-BasuBO
Deciding choreography realizability (SB, TB, MO), pp. 191–202.
VMCAI-2012-BasuBO #communication #verification
Synchronizability for Verification of Asynchronously Communicating Systems (SB, TB, MO), pp. 56–71.
ASE-2011-OsterSB #analysis #automation #requirements
Automating analysis of qualitative preferences in goal-oriented requirements engineering (ZJO, GRS, SB), pp. 448–451.
ASE-2010-HeJBGW #approach #bound #model checking #statistics
A bounded statistical approach for model checking of unbounded until properties (RH, PJ, SB, APG, HW), pp. 225–234.
KR-2010-SanthanamBH #performance #testing
Efficient Dominance Testing for Unconditional Preferences (GRS, SB, VH).
DATE-2009-SinhaRBS #design #multi #protocol #using
Multi-clock Soc design using protocol conversion (RS, PSR, SB, ZS), pp. 123–128.
ESEC-FSE-2009-HannaBR #automation #automaton #behaviour #composition #independence #verification
Behavioral automata composition for automatic topology independent verification of parameterized systems (YH, SB, HR), pp. 325–334.
SPLC-2009-SunLB #composition #requirements #web #web service
Product-line-based requirements customization for web service compositions (HS, RRL, SB), pp. 141–150.
SEKE-2007-VasileB #cost analysis #multi
Cost-based Analysis of Multiple Counter-Examples (FV, SB), pp. 33–38.
TACAS-2006-YangBR #verification #π-calculus
Parameterized Verification of π-Calculus Systems (PY, SB, CRR), pp. 42–57.
TACAS-2005-KellerSBS #c #debugging #model checking #named #source code
FocusCheck: A Tool for Model Checking and Debugging Sequential C Programs (CWK, DS, SB, SAS), pp. 563–569.
SOSP-2003-SekarVBBD #approach #execution
Model-carrying code: a practical approach for safe execution of untrusted applications (RS, VNV, SB, SB, DCD), pp. 15–28.
TACAS-2003-BasuR #analysis #composition #verification
Compositional Analysis for Verification of Parameterized Systems (SB, CRR), pp. 315–330.
TACAS-2002-BasuKPR #model checking #recursion #source code
Resource-Constrained Model Checking of Recursive Programs (SB, KNK, LRP, CRR), pp. 236–250.
ICLP-2001-BasuMRRV #bisimulation #constraints #logic programming #using
Local and Symbolic Bisimulation Using Tabled Constraint Logic Programming (SB, MM, CRR, IVR, RMV), pp. 166–180.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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